LXR coreboot-v3/mainboard/gigabyte/m57sli/initram.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 */
  21
  22#define _MAINOBJECT
  23#include <mainboard.h>
  24#include <types.h>
  25#include <lib.h>
  26#include <console.h>
  27#include <device/device.h>
  28#include <device/pci.h>
  29#include <string.h>
  30#include <msr.h>
  31#include <io.h>
  32#include <cpu.h>
  33#include <globalvars.h>
  34#include <amd/k8/k8.h>
  35#include <southbridge/nvidia/mcp55/mcp55_smbus.h>
  36#include <mc146818rtc.h>
  37#include <spd.h>
  38
  39void hard_reset(void);
  40
  41void memreset_setup(void)
  42{
  43}
  44
  45void memreset(int controllers, const struct mem_controller *ctrl)
  46{
  47}
  48
  49void activate_spd_rom(const struct mem_controller *ctrl)
  50{
  51        /* nothing to do */
  52}
  53
  54
  55/** 
  56  * main for initram for the Gigabyte m57sli.  
  57  */
  58int main(void)
  59{
  60        void enable_smbus(void);
  61        void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn);
  62        void soft_reset_x(unsigned sbbusn, unsigned sbdn);
  63        int cpu_init_detected(unsigned int nodeid);
  64        void start_all_cores(void);
  65        void set_sysinfo_in_ram(unsigned val);
  66        int mcp55_early_setup_x(void);
  67        void soft_reset(void);
  68
  69        struct msr msr;
  70        static const u16 spd_addr[] = {
  71                (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
  72                (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
  73#if CONFIG_MAX_PHYSICAL_CPUS > 1
  74                (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
  75                (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
  76#endif
  77        };
  78        struct sys_info *sysinfo = &(global_vars()->sys_info);
  79
  80        int needs_reset = 0;
  81        unsigned bsp_apicid = 0;
  82        int init_detected;
  83        struct node_core_id me;
  84
  85        me = get_node_core_id();
  86        printk(BIOS_DEBUG, "Hi there from stage1, cpu%d, core%d\n", me.nodeid, me.coreid);
  87
  88        init_detected = cpu_init_detected(me.nodeid);
  89        printk(BIOS_DEBUG, "init_detected: %d\n", init_detected);
  90        /* well, here we are. For starters, we need to know if this is cpu0 core0. 
  91         * cpu0 core 0 will do all the DRAM setup. 
  92         */
  93        bsp_apicid = init_cpus(init_detected, sysinfo);
  94
  95        printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
  96
  97        set_sysinfo_in_ram(0);  // in BSP so could hold all ap until sysinfo is in ram
  98        setup_coherent_ht_domain();     // routing table and start other core0
  99
 100        wait_all_core0_started();
 101#if CONFIG_LOGICAL_CPUS==1
 102        // It is said that we should start core1 after all core0 launched
 103        /* because optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 104         * So here need to make sure last core0 is started, esp for two way system,
 105         * (there may be apic id conflicts in that case)
 106         */
 107        start_all_cores();
 108        wait_all_other_cores_started(bsp_apicid);
 109#endif
 110
 111        /* it will set up chains and store link pair for optimization later */
 112        ht_setup_chains_x(sysinfo);     // it will init sblnk and sbbusn, nodes, sbdn
 113
 114        msr = rdmsr(FIDVID_STATUS);
 115        printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", msr.hi, msr.lo);
 116
 117
 118        enable_fid_change();
 119
 120        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 121
 122        init_fidvid_bsp(bsp_apicid);
 123
 124        msr = rdmsr(FIDVID_STATUS);
 125        printk(BIOS_DEBUG, "end msr fid, vid %08x:%08x\n", msr.hi, msr.lo);
 126
 127
 128        needs_reset |= optimize_link_coherent_ht();
 129        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 130        needs_reset |= mcp55_early_setup_x();
 131
 132        // fidvid change will issue one LDTSTOP and the HT change will be effective too
 133        if (needs_reset) {
 134                printk(BIOS_INFO, "ht reset -\n");
 135                soft_reset();
 136        }
 137
 138        //It's the time to set ctrl in sysinfo now;
 139        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 140
 141        enable_smbus();
 142
 143        memreset_setup();
 144
 145        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 146
 147        /* After RAM is setup allow the APs to do RAM and MTRRs setup if needed. */
 148        allow_all_aps_stop(bsp_apicid);
 149
 150        printk(BIOS_DEBUG, "initram returns\n");
 151        return 0;
 152}
 153
 154