LXR coreboot-v3/mainboard/gigabyte/m57sli/Makefile

   1##
   2## This file is part of the coreboot project.
   3##
   4## Copyright (C) 2006-2007 coresystems GmbH
   5## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
   6##
   7## This program is free software; you can redistribute it and/or modify
   8## it under the terms of the GNU General Public License as published by
   9## the Free Software Foundation; either version 2 of the License, or
  10## (at your option) any later version.
  11##
  12## This program is distributed in the hope that it will be useful,
  13## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15## GNU General Public License for more details.
  16##
  17## You should have received a copy of the GNU General Public License
  18## along with this program; if not, write to the Free Software
  19## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20##
  21
  22STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
  23                        $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
  24                        $(src)/arch/x86/resourcemap.c \
  25                        $(src)/arch/x86/amd/model_fxx/dualcore_id.c \
  26                        $(src)/arch/x86/amd/model_fxx/stage1.c \
  27                        $(src)/northbridge/amd/k8/get_nodes.c \
  28                        $(src)/northbridge/amd/k8/incoherent_ht_chain.c \
  29                        $(src)/northbridge/amd/k8/libstage1.c \
  30                        $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
  31                        $(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \
  32                        $(src)/arch/x86/stage1_mtrr.c
  33
  34STAGE0_DYNAMIC_SRC :=   $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
  35
  36INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
  37                        $(src)/northbridge/amd/k8/raminit.c \
  38                        $(src)/northbridge/amd/k8/dqs.c \
  39                        $(src)/northbridge/amd/k8/reset_test.c \
  40                        $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
  41                        $(src)/northbridge/amd/k8/incoherent_ht.c \
  42                        $(src)/northbridge/amd/k8/coherent_ht.c \
  43                        $(src)/arch/x86/amd/model_fxx/dualcore.c \
  44                        $(src)/arch/x86/amd/model_fxx/fidvid.c \
  45                        $(src)/arch/x86/amd/model_fxx/init_cpus.c \
  46                        $(src)/lib/clog2.c
  47
  48
  49STAGE2_MAINBOARD_SRC = 
  50
  51$(obj)/coreboot.vpd:
  52        $(Q)printf "  BUILD   DUMMY VPD\n"
  53        $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
  54
  55