LXR coreboot-v3/mainboard/artecgroup/dbe63/dts

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21/{
  22        mainboard_vendor = "Artec";
  23        mainboard_name = "DBE63";
  24        cpus { };
  25        apic@0 {
  26                /config/("northbridge/amd/geodelx/apic");
  27        };
  28        domain@0 {
  29                /config/("northbridge/amd/geodelx/domain");
  30                pci@1,0 {
  31                        /config/("northbridge/amd/geodelx/pci");
  32                        /* Video RAM has to be in 2MB chunks. */
  33                        geode_video_mb = "16";
  34                };
  35                pci@1,1 {
  36                        /* This is the graphics device, but since the memory
  37                         * controller needs to know geode_video_mb, the
  38                         * phase2_init is done there.  The rest are default ops.
  39                         */
  40                };
  41                pci@1,2 { /* AES */
  42                };
  43                pci@f,0 {
  44                        /config/("southbridge/amd/cs5536/dts");
  45                        /* Interrupt enables for LPC bus.
  46                         *  Each bit is an IRQ 0-15. */
  47                        lpc_serirq_enable = "0x00001002";
  48                        /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
  49                        lpc_serirq_polarity = "0x0000EFFD";
  50                        /* 0:continuous 1:quiet */
  51                        lpc_serirq_mode = "1";
  52                        /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
  53                         * See virtual PIC spec. */
  54                        enable_gpio_int_route = "0x0D0C0700";
  55                        /* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */
  56                        enable_ide_nand_flash = "2";
  57                        /* we use com2 since that is on the dongle */
  58                        com2_enable = "1";
  59                        /* Set com2 address to be COM1 */
  60                        com2_address = "0x3f8";
  61                        /* Set com2 IRQ to be what is usually COM1 */
  62                        com2_irq = "4";
  63                        /* USB Port Power Handling setting. */
  64                        pph = "0xf5";
  65                };
  66                pci@f,2 {
  67                        /config/("southbridge/amd/cs5536/ide");
  68                };
  69        };
  70};
  71