LXR coreboot-v3/lib/stage2.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Ronald G. Minnich <rminnich@lanl.gov>
   5 * Copyright (C) 2007 coresystems GmbH
   6 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; version 2 of the License.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  20 */
  21
  22/* stage2 - coreboot RAM-based setup. */
  23
  24#include <types.h>
  25#include <string.h>
  26#include <lar.h>
  27#include <console.h>
  28#include <device/device.h>
  29#include <tables.h>
  30#include <globalvars.h>
  31#include <lib.h>
  32
  33/**
  34 * Note that this function has exactly the opposite return code of
  35 * northbridge/intel/i945/reset_test.c which returns 0 on cold boot.
  36 *
  37 * @returns always 1
  38 */
  39int __attribute__((weak)) is_coldboot(void)
  40{
  41        return 1;
  42}
  43
  44/**
  45 * CPU init code which runs BEFORE any stage2 dev_phase1 is run. 
  46 * This code might, for example, init ECC on all cores. 
  47 *
  48 * @param coldboot Is this a power-on coldboot 
  49 * @param sysinfo sysinfo pointer
  50 * @returns 0 on success; error number otherwise
  51 */
  52unsigned int __attribute__((weak)) cpu_phase1(unsigned int coldboot,
  53                        struct sys_info *sysinfo)
  54{
  55        printk(BIOS_SPEW, "cpu_phase1: %s: nothing to do.\n", coldboot? "Coldboot" : "Warmboot");
  56        return 0;
  57}
  58
  59/**
  60 * CPU init code which runs AFTER ALL stage2 dev_phases are run. 
  61 * This code might, for example, install an SMI handler
  62 *
  63 * @param coldboot Is this a power-on coldboot 
  64 * @param sysinfo sysinfo pointer
  65 * @returns 0 on success; error number otherwise
  66 */
  67unsigned int __attribute__((weak)) cpu_phase2(unsigned int coldboot,
  68                        struct sys_info *sysinfo)
  69{
  70        printk(BIOS_SPEW, "cpu_phase2: %s: nothing to do.\n", coldboot? "Coldboot" : "Warmboot");
  71        return 0;
  72}
  73
  74/**
  75 * Main function of the DRAM part of coreboot.
  76 *
  77 * Coreboot is divided into pre-DRAM part and DRAM part. The stages before
  78 * this part are stage 0 and stage 1. This part contains stage 2, which
  79 * consists of phases 1 through 6.
  80 * printk has been set up in stage 1 and is working.
  81 *
  82 * Device Enumeration: in the dev_enumerate() phase.
  83 *
  84 * TODO:
  85 * - Check whether this documentation is still correct. Improve it.
  86 */
  87void *stage2(void)
  88{
  89        void *mbi;
  90        struct sys_info *sysinfo;
  91        struct global_vars *global_vars(void);
  92        post_code(POST_STAGE2_BEGIN);
  93        sysinfo = &(global_vars()->sys_info);
  94        cpu_phase1(is_coldboot(), sysinfo);
  95        dev_init();
  96
  97        /* Phase 1 was console init and making printk work. Both functions are
  98         * now performed by stage 1 code. Phase 1 is now without purpose.
  99         */
 100        post_code(POST_STAGE2_PHASE1_START);
 101        dev_phase1();
 102        show_all_devs(BIOS_DEBUG, "After phase 1.");
 103
 104        /* Here is where weird stuff like init_timer handling should be
 105         * done. This is for ANYTHING that might have to happen before
 106         * device enumeration but that needs a printk.
 107         */
 108        post_code(POST_STAGE2_PHASE2_START);
 109        dev_phase2();
 110        show_all_devs(BIOS_DEBUG, "After phase 2.");
 111
 112        /* Walk physical devices and add any dynamic devices to the
 113         * device tree.
 114         */
 115        post_code(POST_STAGE2_PHASE3_START);
 116        dev_root_phase3();
 117        show_all_devs_tree(BIOS_DEBUG, "After phase 3.");
 118
 119        /* Compute and assign the bus resources. */
 120        post_code(POST_STAGE2_PHASE4_START);
 121        dev_phase4();
 122        show_all_devs(BIOS_DEBUG, "After phase 4.");
 123
 124        /* Now actually enable devices on the bus. */
 125        post_code(POST_STAGE2_PHASE5_START);
 126        dev_root_phase5();
 127        show_all_devs(BIOS_DEBUG, "After phase 5.");
 128
 129        /* Initialize devices on the bus. */
 130        post_code(POST_STAGE2_PHASE6_START);
 131        dev_phase6();
 132        show_all_devs(BIOS_DEBUG, "After phase 6.");
 133
 134        cpu_phase2(is_coldboot(), sysinfo);
 135
 136        /* Write tables to pass information to the payloads. */
 137        post_code(POST_STAGE2_WRITE_TABLES);
 138        mbi = write_tables();
 139        show_all_devs(BIOS_DEBUG, "After writing tables.");
 140
 141        return mbi;
 142}
 143
 144EXPORT_SYMBOL(stage2);
 145