LXR coreboot-v2/src/superio/smsc/smscsuperio/superio.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21/*
  22 * Generic driver for pretty much all known Standard Microsystems Corporation
  23 * (SMSC) Super I/O chips.
  24 *
  25 * Datasheets are available from: http://www.smsc.com/main/datasheet.html
  26 *
  27 * Most of the SMSC Super I/O chips seem to be similar enough (for our
  28 * purposes) so that we can handle them with a unified driver.
  29 *
  30 * So far only the ASUS A8000 has been tested on real hardware!
  31 *
  32 * The floppy disk controller, the parallel port, the serial ports, and the
  33 * keyboard controller should work with all the chips. For the more advanced
  34 * stuff (e.g. HWM, ACPI, SMBus) more work is probably required.
  35 */
  36
  37#include <arch/io.h>
  38#include <device/device.h>
  39#include <device/pnp.h>
  40#include <console/console.h>
  41#include <uart8250.h>
  42#include <pc80/keyboard.h>
  43#include <stdlib.h>
  44#include "chip.h"
  45
  46/* The following Super I/O chips are currently supported by this driver: */
  47#define LPC47M172       0x14
  48#define FDC37B80X       0x42    /* Same ID: FDC37M70X (a.k.a. FDC37M707) */
  49#define FDC37B78X       0x44
  50#define FDC37B72X       0x4c
  51#define FDC37M81X       0x4d
  52#define FDC37M60X       0x47
  53#define LPC47B27X       0x51    /* a.k.a. LPC47B272 */
  54#define LPC47U33X       0x54
  55#define LPC47M10X       0x59    /* Same ID: LPC47M112, LPC47M13X */
  56#define LPC47M15X       0x60    /* Same ID: LPC47M192 */
  57#define LPC47S45X       0x62
  58#define LPC47B397       0x6f
  59#define A8000           0x77    /* ASUS A8000, a rebranded DME1737(?) */
  60#define DME1737         0x78
  61#define SCH3112         0x7c
  62#define SCH5307         0x81    /* Rebranded LPC47B397(?) */
  63#define SCH5027D        0x89
  64
  65/* Register defines */
  66#define DEVICE_ID_REG   0x20    /* Device ID register */
  67#define DEVICE_REV_REG  0x21    /* Device revision register */
  68#define DEVICE_TEST7_REG 0x29   /* Device test 7 register */
  69
  70/* Static variables for the Super I/O device ID and revision. */
  71static int first_time = 1;
  72static uint8_t superio_id = 0;
  73static uint8_t superio_rev = 0;
  74
  75/**
  76 * A list of all possible logical devices which may be supported by at least
  77 * one of the Super I/O chips. These values are used as index into the
  78 * logical_device_table[i].devs array(s).
  79 *
  80 * If you change this enum, you must also adapt the logical_device_table[]
  81 * array and MAX_LOGICAL_DEVICES!
  82 */
  83enum {
  84        LD_FDC,         /* Floppy disk controller */
  85        LD_PP,          /* Parallel port */
  86        LD_SP1,         /* Serial port 1 (COM1) */
  87        LD_SP2,         /* Serial port 2 (COM2) */
  88        LD_RTC,         /* Real-time clock */
  89        LD_KBC,         /* Keyboard controller */
  90        LD_AUX,         /* Auxiliary I/O */
  91        LD_XBUS,        /* X-Bus */
  92        LD_HWM,         /* Hardware monitor */
  93        LD_GAME,        /* Game port */
  94        LD_PME,         /* Power management events */
  95        LD_MPU401,      /* MPU-401 MIDI UART */
  96        LD_RT,          /* Runtime registers / security key registers */
  97        LD_ACPI,        /* ACPI */
  98        LD_SMB,         /* SMBus */
  99};
 100
 101/* Note: This value must match the number of items in the enum above! */
 102#define MAX_LOGICAL_DEVICES 15
 103
 104/**
 105 * A table describing the logical devices which are present on the
 106 * supported Super I/O chips.
 107 *
 108 * The first entry (superio_id) is the device ID of the Super I/O chip
 109 * as stored in the (read-only) DEVICE_ID_REG register.
 110 *
 111 * The second entry (devs) is the list of logical device IDs which are
 112 * present on that particular Super I/O chip. A value of -1 means the
 113 * device is not present on that chip.
 114 *
 115 * Note: Do _not_ list chips with different name but same device ID twice!
 116 *       The result would be that the init code would be executed twice!
 117 */
 118static const struct logical_devices {
 119        uint8_t superio_id;
 120        int devs[MAX_LOGICAL_DEVICES];
 121} logical_device_table[] = {
 122        // Chip   FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
 123        {LPC47M172,{0, 3, 4,  2, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 124        {FDC37B80X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
 125        {FDC37B78X,{0, 3, 4,  5,  6,  7,  8,  -1, -1,  -1, -1, -1, -1, 10, -1}},
 126        {FDC37B72X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, 10, -1}},
 127        {FDC37M81X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
 128        {FDC37M60X,{0, 3, 4,  5, -1,  7,  8,  -1, -1,  -1, -1, -1, -1, -1, -1}},
 129        {LPC47B27X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, -1, 11, 10, -1, -1}},
 130        {LPC47M10X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, 10, 11, -1, -1, -1}},
 131        {LPC47M15X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, 10, 11, -1, -1, -1}},
 132        {LPC47S45X,{0, 3, 4,  5,  6,  7, -1,   8, -1,  -1, -1, -1, 10, -1, 11}},
 133        {LPC47B397,{0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
 134        {LPC47U33X,{0, 3, 4, -1, -1,  7, -1,  -1, -1,   9,  0,  5, 10,  0, 11}},
 135        {A8000,    {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 136        {DME1737,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 137        {SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 138        {SCH5307,  {0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
 139        {SCH5027D, {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, 11}},
 140};
 141
 142/**
 143 * Enter the configuration state by writing 0x55 to the config port.
 144 *
 145 * The Super I/O configuration registers can only be modified when the chip
 146 * is in the configuration state. Thus, to program the registers you have
 147 * to a) enter config mode, b) program the registers, c) exit config mode.
 148 *
 149 * @param dev The device to use.
 150 */
 151static inline void smsc_pnp_enter_conf_state(device_t dev)
 152{
 153        outb(0x55, dev->path.pnp.port);
 154}
 155
 156/**
 157 * Exit the configuration state by writing 0xaa to the config port.
 158 *
 159 * This puts the chip into the 'run' state again.
 160 *
 161 * @param dev The device to use.
 162 */
 163static inline void smsc_pnp_exit_conf_state(device_t dev)
 164{
 165        outb(0xaa, dev->path.pnp.port);
 166}
 167
 168/** Wrapper for pnp_set_resources(). */
 169static void smsc_pnp_set_resources(device_t dev)
 170{
 171        smsc_pnp_enter_conf_state(dev);
 172        pnp_set_resources(dev);
 173        smsc_pnp_exit_conf_state(dev);
 174}
 175
 176/** Wrapper for pnp_enable_resources(). */
 177static void smsc_pnp_enable_resources(device_t dev)
 178{
 179        smsc_pnp_enter_conf_state(dev);
 180        pnp_enable_resources(dev);
 181        smsc_pnp_exit_conf_state(dev);
 182}
 183
 184/**
 185 * If so configured, enable the specified device, otherwise
 186 * explicitly disable it.
 187 *
 188 * @param dev The device to use.
 189 */
 190static void smsc_pnp_enable(device_t dev)
 191{
 192        smsc_pnp_enter_conf_state(dev);
 193        pnp_set_logical_device(dev);
 194        (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
 195        smsc_pnp_exit_conf_state(dev);
 196}
 197
 198/**
 199 * Initialize those logical devices which need a special init.
 200 *
 201 * @param dev The device to use.
 202 */
 203static void smsc_init(device_t dev)
 204{
 205        struct superio_smsc_smscsuperio_config *conf = dev->chip_info;
 206        struct resource *res0, *res1;
 207        int i, ld;
 208
 209        /* Do not initialize disabled devices. */
 210        if (!dev->enabled)
 211                return;
 212
 213        /* Find the correct Super I/O. */
 214        for (i = 0; i < ARRAY_SIZE(logical_device_table); i++)
 215                if (logical_device_table[i].superio_id == superio_id)
 216                        break;
 217
 218        /* If no Super I/O was found, return. */
 219        if (i == ARRAY_SIZE(logical_device_table))
 220                return;
 221
 222        /* A Super I/O was found, so initialize the respective device. */
 223        ld = dev->path.pnp.device;
 224        if (ld == logical_device_table[i].devs[LD_SP1]) {
 225                res0 = find_resource(dev, PNP_IDX_IO0);
 226                init_uart8250(res0->base, &conf->com1);
 227        } else if (ld == logical_device_table[i].devs[LD_SP2]) {
 228                res0 = find_resource(dev, PNP_IDX_IO0);
 229                init_uart8250(res0->base, &conf->com2);
 230        } else if (ld == logical_device_table[i].devs[LD_KBC]) {
 231                res0 = find_resource(dev, PNP_IDX_IO0);
 232                res1 = find_resource(dev, PNP_IDX_IO1);
 233                init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 234        }
 235}
 236
 237/** Standard device operations. */
 238static struct device_operations ops = {
 239        .read_resources         = pnp_read_resources,
 240        .set_resources          = smsc_pnp_set_resources,
 241        .enable_resources       = smsc_pnp_enable_resources,
 242        .enable                 = smsc_pnp_enable,
 243        .init                   = smsc_init,
 244};
 245
 246/**
 247 * TODO.
 248 *
 249 * This table should contain all possible entries for any of the supported
 250 * Super I/O chips, even if some of them don't have the respective logical
 251 * devices. That will be handled correctly by our code.
 252 *
 253 * The LD_FOO entries are device markers which tell you the type of the logical
 254 * device (e.g. whether it's a floppy disk controller or a serial port etc.).
 255 *
 256 * Before using pnp_dev_info[] in pnp_enable_devices() these markers have
 257 * to be replaced with the real logical device IDs of the respective
 258 * Super I/O chip. This is done in enable_dev().
 259 *
 260 * TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet).
 261 */
 262static struct pnp_info pnp_dev_info[] = {
 263        { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
 264        { &ops, LD_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
 265        { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 266        { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 267        { &ops, LD_RTC, },
 268        { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 },
 269                                                                 { 0x7ff, 4 },},
 270        { &ops, LD_AUX, },
 271        { &ops, LD_XBUS, },
 272        { &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, },
 273        { &ops, LD_GAME, },
 274        { &ops, LD_PME, },
 275        { &ops, LD_MPU401, },
 276        { &ops, LD_RT,  PNP_IO0, { 0x780, 0 }, },
 277        { &ops, LD_ACPI, },
 278        { &ops, LD_SMB, },
 279};
 280
 281/**
 282 * Enable the logical devices of the Super I/O chip.
 283 *
 284 * TODO: Think about how to handle the case when a mainboard has multiple
 285 *       Super I/O chips soldered on.
 286 * TODO: Can this code be simplified a bit?
 287 *
 288 * @param dev The device to use.
 289 */
 290static void enable_dev(device_t dev)
 291{
 292        int i, j, fn;
 293        int tmp[MAX_LOGICAL_DEVICES];
 294        uint8_t test7;
 295
 296        if (first_time) {
 297                /* Read the device ID and revision of the Super I/O chip. */
 298                smsc_pnp_enter_conf_state(dev);
 299                superio_id = pnp_read_config(dev, DEVICE_ID_REG);
 300                superio_rev = pnp_read_config(dev, DEVICE_REV_REG);
 301                smsc_pnp_exit_conf_state(dev);
 302
 303                /* TODO: Error handling? */
 304
 305                printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
 306                            superio_id, superio_rev);
 307                first_time = 0;
 308
 309                if(superio_id == LPC47M172) {
 310                  /* Do not use the default logical device number
 311                   * but instead the standard smsc registers set
 312                   */
 313
 314                  /* TEST7 configuration register (0x29)
 315                   * bit 0 : LD_NUM (0 = new, 1 = std smsc)
 316                   */
 317                  test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
 318                  test7 |= 1;
 319                  pnp_write_config(dev, DEVICE_TEST7_REG, test7);
 320                }
 321        }
 322
 323        /* Find the correct Super I/O. */
 324        for (i = 0; i < ARRAY_SIZE(logical_device_table); i++)
 325                if (logical_device_table[i].superio_id == superio_id)
 326                        break;
 327
 328        /* If no Super I/O was found, return. */
 329        if (i == ARRAY_SIZE(logical_device_table))
 330                return;
 331
 332        /* Temporarily save the LD_FOO values. */
 333        for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
 334                tmp[j] = pnp_dev_info[j].function;
 335
 336        /* Replace the LD_FOO markers in pnp_dev_info[] with
 337         * the real logical device IDs of this Super I/O chip.
 338         */
 339        for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) {
 340                fn = pnp_dev_info[j].function;
 341                pnp_dev_info[j].function = logical_device_table[i].devs[fn];
 342        }
 343
 344        /* Enable the specified devices (if present on the chip). */
 345        pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
 346                           &pnp_dev_info);
 347
 348        /* Restore LD_FOO values. */
 349        for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
 350                pnp_dev_info[j].function = tmp[j];
 351}
 352
 353struct chip_operations superio_smsc_smscsuperio_ops = {
 354        CHIP_NAME("Various SMSC Super I/Os")
 355        .enable_dev = enable_dev
 356};
 357