1/* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2007 AMD 5 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22#ifndef MCP55_CHIP_H 23#define MCP55_CHIP_H 24 25struct southbridge_nvidia_mcp55_config 26{ 27 unsigned int ide0_enable : 1; 28 unsigned int ide1_enable : 1; 29 unsigned int sata0_enable : 1; 30 unsigned int sata1_enable : 1; 31 unsigned int mac_eeprom_smbus; 32 unsigned int mac_eeprom_addr; 33}; 34struct chip_operations; 35extern struct chip_operations southbridge_nvidia_mcp55_ops; 36 37#endif /* MCP55_CHIP_H */ 38