LXR coreboot-v2/src/northbridge/via/vx800/uma_ram

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19
  20#include "pci_rawops.h"
  21
  22typedef struct __UMA_RAM_tag {
  23        u16 DramSize;
  24        u8 D0F3Val;
  25        u8 D1F0Val;
  26        u8 VgaPortVal;
  27} UMARAM;
  28#define UMARAM_512M     7
  29#define UMARAM_256M     6
  30#define UMARAM_128M     5
  31#define UMARAM_64M      4
  32#define UMARAM_32M      3
  33#define UMARAM_16M      2
  34#define UMARAM_8M       1
  35#define UMARAM_0M       0
  36
  37#define FB_512M         0
  38#define FB_256M         0x40
  39#define FB_128M         0x60
  40#define FB_64M          0x70
  41#define FB_32M          0x78
  42#define FB_16M          0x7c
  43#define FB_8M           0x7E
  44#define FB_4M           0x7F
  45
  46#define VGA_PORT_512M   0x00
  47#define VGA_PORT_256M   0x80
  48#define VGA_PORT_128M   0xC0
  49#define VGA_PORT_64M    0xE0
  50#define VGA_PORT_32M    0xF0
  51#define VGA_PORT_16M    0xF8
  52
  53#define VIACONFIG_VGA_PCI_10 0xf8000008
  54#define VIACONFIG_VGA_PCI_14 0xfc000000
  55
  56static const UMARAM UMARamArr[] = {
  57        {0, UMARAM_0M, FB_4M, 0xFE},
  58        {8, UMARAM_8M, FB_8M, 0xFC},
  59        {16, UMARAM_16M, FB_16M, VGA_PORT_16M},
  60        {32, UMARAM_32M, FB_32M, VGA_PORT_32M},
  61        {64, UMARAM_64M, FB_64M, VGA_PORT_64M},
  62        {128, UMARAM_128M, FB_128M, VGA_PORT_128M},
  63        {256, UMARAM_256M, FB_256M, VGA_PORT_256M},
  64        {512, UMARAM_512M, FB_512M, VGA_PORT_512M},
  65        {0xffff, 0xff, 0xff, 0xFF}
  66};
  67
  68void SetUMARam(void)
  69{
  70#if 1
  71        u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
  72        device_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0);
  73        u8 ByteVal, temp;
  74        UMARAM *pUMARamTable;
  75        u16 UmaSize;
  76        u8 SLD0F3Val, SLD1F0Val, VgaPortVal;
  77        u32 RamSize, SLBase, Tmp;
  78        u8 i;
  79        PRINT_DEBUG_MEM("Entering vx800 SetUMARam.\n");
  80        SLD0F3Val = 0;
  81        SLD1F0Val = 0;
  82        VgaPortVal = 0;
  83
  84        ByteVal = pci_read_config8(MEMCTRL, 0xa1);
  85        ByteVal |= 0x80;
  86        pci_write_config8(MEMCTRL, 0xa1, ByteVal);
  87
  88        //set VGA Timer
  89        pci_write_config8(MEMCTRL, 0xa2, 0xee);
  90
  91        //set agp misc
  92        //GFX Data Delay to Sync with Clock
  93        pci_write_config8(MEMCTRL, 0xa4, 0x01);
  94
  95        //page register life timer
  96        pci_write_config8(MEMCTRL, 0xa6, 0x76);
  97
  98        //GMINT and GFX relatate
  99        //note Bit 3 VGA Enable
 100        pci_write_config8(MEMCTRL, 0xa7, 0x8c);
 101        // ByteVal = 0x4c;
 102
 103        //GMINT Misc.1
 104        //pci_write_config8(MEMCTRL, 0xb0, 0x80);
 105
 106        //pci_write_config8(MEMCTRL, 0xb1, 0xaa);
 107
 108        //AGPCINT MISC
 109        //pci_write_config8(MEMCTRL, 0xb2, 0x82);
 110        //ByteVal = 0x8A;
 111
 112        //GMINT MISC.2
 113        //disable read pass write
 114        pci_write_config8(MEMCTRL, 0xb3, 0x9A);
 115
 116        //EPLL Register
 117        //pci_write_config8(MEMCTRL, 0xb4, 0x04);
 118
 119        //enable CHA and CHB merge mode
 120        pci_write_config8(MEMCTRL, 0xde, 0x06);
 121
 122        //if can get the value from setup interface, so get the value
 123        //else use the default value
 124        UmaSize = CONFIG_VIDEO_MB;
 125
 126        for (pUMARamTable = UMARamArr; pUMARamTable->DramSize != 0xffff;
 127             pUMARamTable++) {
 128                if (UmaSize == pUMARamTable->DramSize) {
 129                        SLD0F3Val = pUMARamTable->D0F3Val;
 130                        SLD1F0Val = pUMARamTable->D1F0Val;
 131                        VgaPortVal = pUMARamTable->VgaPortVal;
 132                }
 133        }
 134        //set SL size
 135        //Fill in Fun3_RXA1[6:4] with the Frame Buffer size for the Integrated Graphic Device.
 136        ByteVal = pci_read_config8(MEMCTRL, 0xa1);
 137        ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4);
 138        pci_write_config8(MEMCTRL, 0xa1, ByteVal);
 139
 140//      vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0);
 141
 142        //RxB2 may be for S.L. and RxB1 may be for L. L. 
 143        // It is different from Spec.
 144        ByteVal = SLD1F0Val;
 145        pci_write_config8(vga_dev, 0xb2, ByteVal);
 146
 147        //set M1 size
 148        //ByteVal=pci_read_config8(MEMCTRL, 0xa3);
 149        //ByteVal = 0x02;
 150        //pci_write_config8(MEMCTRL, 0xa3, ByteVal);
 151
 152        PRINT_DEBUG_MEM("UMA setting - 3\n");
 153
 154        //Enable p2p  IO/mem
 155        ByteVal = 0x07;
 156        pci_write_config8(vga_dev, 0x04, ByteVal);
 157
 158        //must set SL and MMIO base, or else when enable GFX memory space, system will hang
 159        //set S.L base
 160        Tmp = pci_read_config32(vga_dev, 0x10);
 161        Tmp = 0xfffffff8;
 162        pci_write_config32(vga_dev, 0x10, Tmp);
 163        Tmp = pci_read_config32(vga_dev, 0x10);
 164        Tmp = VIACONFIG_VGA_PCI_10;
 165        pci_write_config32(vga_dev, 0x10, Tmp);
 166
 167        //set MMIO base
 168        Tmp = pci_read_config32(vga_dev, 0x14);
 169        Tmp = 0xfffffffC;
 170        pci_write_config32(vga_dev, 0x14, Tmp);
 171        Tmp = pci_read_config32(vga_dev, 0x14);
 172        Tmp = VIACONFIG_VGA_PCI_14;
 173        pci_write_config32(vga_dev, 0x14, Tmp);
 174
 175//enable direct cpu frame buffer access
 176        i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1);
 177        i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
 178        pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i);
 179        pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01);
 180
 181        //enable GFx memory space access control for S.L and mmio
 182        ByteVal = pci_read_config8(d0f0_dev, 0xD4);
 183        ByteVal |= 0x03;
 184        //ByteVal |= 0x01;
 185        pci_write_config8(d0f0_dev, 0xD4, ByteVal);
 186
 187        //enable Base VGA 16 Bits Decode
 188        ByteVal = pci_read_config8(d0f0_dev, 0xfe);
 189        ByteVal |= 0x10;
 190        pci_write_config8(d0f0_dev, 0xfe, ByteVal);
 191
 192        //disable CHB L.L
 193        //set VGA memory selection
 194        ByteVal = pci_read_config8(vga_dev, 0xb0);
 195        ByteVal &= 0xF8;
 196        //ByteVal |= 0x01;
 197        ByteVal |= 0x03;
 198        pci_write_config8(vga_dev, 0xb0, ByteVal);
 199
 200        //set LL size
 201
 202        //enable memory access to SL,MMIO,LL and IO to 3B0~3BB,3C0 ~3DF
 203        //ByteVal = 0x03;
 204        //pci_write_config8(d0f0_dev, 0xc0, ByteVal);
 205
 206        //Turn on Graphic chip IO port port access
 207        ByteVal = inb(0x03C3);
 208        ByteVal |= 0x01;
 209        outb(ByteVal, 0x03C3);
 210
 211        //Turn off Graphic chip Register protection
 212        outb(0x10, 0x03C4);
 213
 214        ByteVal = inb(0x03C5);
 215        ByteVal |= 0x01;
 216        outb(ByteVal, 0x03C5);
 217
 218        //set VGA memory Frequence
 219        //direct IO port 0x3DX to vga io space 0x3C2[0]
 220        ByteVal = inb(0x03CC);
 221        ByteVal |= 0x03;
 222        outb(ByteVal, 0x03C2);
 223        //  ByteVal=inb(0x03C2);
 224        //   ByteVal |= 0x01;
 225        //   outb(ByteVal,0x03C2);
 226
 227#if 1                           //bios porting guide has no this two defination:  3d  on 3d4/3d5 and  39 on 3c4/3c5
 228        //set frequence 0x3D5.3d[7:4]
 229        outb(0x3d, 0x03d4);
 230
 231        temp = pci_read_config8(MEMCTRL, 0x90);
 232        temp = (u8) (temp & 0x07);
 233        ByteVal = inb(0x03d5);
 234        switch (temp) {
 235        case 0:         //DIMMFREQ_200:
 236                ByteVal = (u8) ((ByteVal & 0x0F) | 0x30);
 237                break;
 238        case 1:         //DIMMFREQ_266:
 239                ByteVal = (u8) ((ByteVal & 0x0F) | 0x40);
 240                break;
 241        case 3:         //DIMMFREQ_400:
 242                ByteVal = (u8) ((ByteVal & 0x0F) | 0x60);
 243                break;
 244        case 4:         //DIMMFREQ_533:
 245                ByteVal = (u8) ((ByteVal & 0x0F) | 0x70);
 246                break;
 247        case 5:         //DIMMFREQ_667:
 248                ByteVal = (u8) ((ByteVal & 0x0F) | 0x80);
 249                break;
 250        case 6:         //DIMMFREQ_800:
 251                ByteVal = (u8) ((ByteVal & 0x0F) | 0x90);
 252                break;
 253        default:
 254                ByteVal = (u8) ((ByteVal & 0x0F) | 0x70);
 255                break;
 256        }
 257        outb(ByteVal, 0x03d5);
 258
 259        // Set frame buffer size 
 260        outb(0x39, 0x03c4);
 261        outb(1 << SLD0F3Val, 0x03c5);
 262
 263#endif
 264        // Set S.L. size in GFX's register
 265        outb(0x68, 0x03c4);
 266        outb(VgaPortVal, 0x03c5);
 267
 268        //  ECLK Selection (00:166Mhz, 01:185Mhz, 10:250Mhz, 11:275Mhz)
 269        // set 3C5.5A[0]=1, address maps to secondary resgiters
 270        outb(0x5a, 0x03c4);
 271        ByteVal = inb(0x03c5);
 272        ByteVal |= 0x01;
 273        outb(ByteVal, 0x03c5);
 274
 275        // Set 3D5.4C[7:6] (00:166Mhz, 01:185Mhz, 10:250Mhz, 11:275Mhz)
 276        outb(0x4c, 0x03d4);
 277        ByteVal = inb(0x03d5);
 278        ByteVal = (ByteVal & 0x3F) | 0x80;
 279        outb(ByteVal, 0x03d5);
 280
 281        // set 3C5.5A[0]=0, address maps to first resgiters
 282        outb(0x5a, 0x03c4);
 283        ByteVal = inb(0x03c5);
 284        ByteVal &= 0xFE;
 285        outb(ByteVal, 0x03c5);
 286
 287        // Set S.L. Address in System Memory
 288        //calculate dram size
 289        for (RamSize = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 290                RamSize = pci_read_config8(MEMCTRL, ramregs[i]);
 291                if (RamSize != 0)
 292                        break;
 293        }
 294        //calculate SL Base Address
 295        SLBase = (RamSize << 26) - (UmaSize << 20);
 296
 297        outb(0x6D, 0x03c4);
 298        //SL Base[28:21] 
 299        outb((u8) ((SLBase >> 21) & 0xFF), 0x03c5);
 300
 301        outb(0x6e, 0x03c4);
 302        //SL Base[36:29]
 303        outb((u8) ((SLBase >> 29) & 0xFF), 0x03c5);
 304
 305        outb(0x6f, 0x03c4);
 306        outb(0x00, 0x03c5);
 307
 308        // Set SVID high byte
 309        outb(0x36, 0x03c4);
 310        outb(0x11, 0x03c5);
 311
 312        // Set SVID Low byte
 313        outb(0x35, 0x03c4);
 314        outb(0x06, 0x03c5);
 315
 316        // Set SID high byte
 317        outb(0x38, 0x03c4);
 318        outb(0x51, 0x03c5);
 319
 320        // Set SID Low byte
 321        outb(0x37, 0x03c4);
 322        outb(0x22, 0x03c5);
 323
 324        //start : For enable snapshot mode control
 325        // program 3C5 for SNAPSHOT Mode control, set RxF3h=1Ah
 326        outb(0xf3, 0x03c4);
 327        ByteVal = inb(0x03c5);
 328        ByteVal = (ByteVal & 0xE5) | 0x1A;
 329        outb(ByteVal, 0x03c5);
 330
 331        outb(0xf3, 0x03d4);
 332        ByteVal = inb(0x03d5);
 333        ByteVal = (ByteVal & 0xE5) | 0x1A;
 334        outb(ByteVal, 0x03d5);
 335
 336        u8 table3c43c5[0x70] = {
 337                0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00,
 338                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 339                0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F,
 340                0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00,
 341                0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00,
 342                0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC,
 343                0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22,
 344                0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF,
 345                0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D,
 346                0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F,
 347                0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00,
 348                0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00,
 349                0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20,
 350                0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00
 351        };
 352        u8 table3d43d5[0x88] = {
 353                0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0,
 354                0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 355                0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3,
 356                0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 357                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 358                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 359                0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34,
 360                0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00,
 361                0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01,
 362                0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00,
 363                0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
 364                0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
 365                0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10,
 366                0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D,
 367                0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00,
 368                0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
 369                0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
 370        };
 371
 372        u8 table3c0space[0xc0] = {
 373                0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00,
 374                0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00,
 375                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 376                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 377                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 378                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 379                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF,
 380                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 381                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 382                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 383                0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
 384                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 385                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 386                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 387                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 388                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 389                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 390                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 391                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 392                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 393                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 394                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 395                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 396                0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 397        };
 398#if 0
 399//for(i=0;i<0xc0;i++)
 400        for (i = 0; i < 0x40; i++)      //
 401        {
 402                outb(table3c0space[i], 0x03c0 + i);
 403        }
 404
 405        for (i = 0; i < 0x70; i++) {
 406                outb(i, 0x03c4);
 407                outb(table3c43c5[i], 0x03c5);
 408        }
 409        for (i = 0; i < 0x88; i++) {
 410                outb(i, 0x03d4);
 411                outb(table3d43d5[i], 0x03d5);
 412        }
 413        outb(0x92, 0x03d4);
 414        outb(0x80, 0x03d5);
 415
 416        outb(0xa3, 0x03d4);
 417        outb(0x00, 0x03d5);
 418
 419        outb(0xe8, 0x03d4);
 420        outb(0x40, 0x03d5);
 421#endif
 422//3d4 3d freq
 423//IO Port / Index: 3X5.3D
 424//Scratch Pad Register 4
 425
 426//    outb(0x39,0x03c4);//
 427        //outb(1 << SLD0F3Val ,0x03c5);
 428//
 429#endif
 430
 431}
 432