LXR coreboot-v2/src/northbridge/amd/amdfam10/raminit_sysinfo_in

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19
  20
  21static void set_htic_bit(u8 i, u32 val, u8 bit)
  22{
  23        u32 dword;
  24        dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL);
  25        dword &= ~(1<<bit);
  26        dword |= ((val & 1) <<bit);
  27        pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword);
  28}
  29
  30
  31static u32 get_htic_bit(u8 i, u8 bit)
  32{
  33        u32 dword;
  34        dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL);
  35        dword &= (1<<bit);
  36        return dword;
  37}
  38
  39static void wait_till_sysinfo_in_ram(void)
  40{
  41        while(1) {
  42                /* give the NB a break, many CPUs spinning on one bit makes a
  43                 * lot of traffic and time is not too important to APs.
  44                 */
  45                udelay_tsc(1000);
  46                if(get_htic_bit(0, 9)) return;
  47        }
  48}
  49
  50static void set_sysinfo_in_ram(u32 val)
  51{
  52        set_htic_bit(0, val, 9);
  53}
  54
  55static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr)
  56{
  57        int i;
  58        int j;
  59        int index = 0;
  60        struct mem_controller *ctrl;
  61        for(i=0;i<controllers; i++) {
  62                ctrl = &ctrl_a[i];
  63                ctrl->node_id = i;
  64                ctrl->f0 = NODE_PCI(i, 0);
  65                ctrl->f1 = NODE_PCI(i, 1);
  66                ctrl->f2 = NODE_PCI(i, 2);
  67                ctrl->f3 = NODE_PCI(i, 3);
  68                ctrl->f4 = NODE_PCI(i, 4);
  69                ctrl->f5 = NODE_PCI(i, 5);
  70
  71                if(spd_addr == (void *)0) continue;
  72
  73                ctrl->spd_switch_addr = spd_addr[index++];
  74
  75                for(j=0; j < 8; j++) {
  76                        ctrl->spd_addr[j] = spd_addr[index++];
  77
  78                }
  79        }
  80}
  81
  82