LXR coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2006 AMD
   5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 *
   7 * Copyright (C) 2006 MSI
   8 * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23 */
  24
  25#define ASSEMBLY 1
  26#define __ROMCC__
  27
  28#define RAMINIT_SYSINFO 1
  29#define CACHE_AS_RAM_ADDRESS_DEBUG 0
  30
  31#define SET_NB_CFG_54 1
  32
  33//used by raminit
  34#define QRANK_DIMM_SUPPORT 1
  35
  36//used by init_cpus and fidvid
  37#define K8_SET_FIDVID 1
  38//if we want to wait for core1 done before DQS training, set it to 0
  39#define K8_SET_FIDVID_CORE0_ONLY 1
  40
  41#define DEBUG_SMBUS 1
  42
  43#include <stdint.h>
  44#include <string.h>
  45#include <device/pci_def.h>
  46#include <arch/io.h>
  47#include <device/pnp_def.h>
  48#include <arch/romcc_io.h>
  49#include <cpu/x86/lapic.h>
  50#include "option_table.h"
  51#include "pc80/mc146818rtc_early.c"
  52#include "pc80/serial.c"
  53#include "arch/i386/lib/console.c"
  54
  55#include <cpu/amd/model_fxx_rev.h>
  56#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  57#include "northbridge/amd/amdk8/raminit.h"
  58#include "cpu/amd/model_fxx/apic_timer.c"
  59#include "lib/delay.c"
  60
  61#include "cpu/x86/lapic/boot_cpu.c"
  62#include "northbridge/amd/amdk8/reset_test.c"
  63#include "northbridge/amd/amdk8/debug.c"
  64#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  65
  66#include "cpu/amd/mtrr/amd_earlymtrr.c"
  67#include "cpu/x86/bist.h"
  68
  69#include "northbridge/amd/amdk8/setup_resource_map.c"
  70
  71#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  72#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  73
  74#include <device/pci_ids.h>
  75#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  76static void memreset_setup(void)
  77{
  78}
  79
  80static void memreset(int controllers, const struct mem_controller *ctrl)
  81{
  82}
  83
  84static inline void activate_spd_rom(const struct mem_controller *ctrl)
  85{
  86#define SMBUS_SWITCH1 0x70
  87#define SMBUS_SWITCH2 0x72
  88        unsigned device=(ctrl->channel0[0])>>8;
  89        smbus_send_byte(SMBUS_SWITCH1, device);
  90       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  91}
  92
  93#if 0
  94static inline void change_i2c_mux(unsigned device)
  95{
  96#define SMBUS_SWITCH1 0x70
  97#define SMBUS_SWITHC2 0x72
  98        smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  99       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
 100}
 101#endif
 102
 103static inline int spd_read_byte(unsigned device, unsigned address)
 104{
 105       return smbus_read_byte(device, address);
 106}
 107
 108//#define K8_4RANK_DIMM_SUPPORT 1
 109
 110#include "northbridge/amd/amdk8/amdk8_f.h"
 111#include "northbridge/amd/amdk8/raminit_f.c"
 112#include "northbridge/amd/amdk8/coherent_ht.c"
 113#include "northbridge/amd/amdk8/incoherent_ht.c"
 114#include "lib/generic_sdram.c"
 115
 116 /* msi does not want the default */
 117#include "resourcemap.c"
 118#include "cpu/amd/dualcore/dualcore.c"
 119
 120#define MCP55_NUM 1
 121#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 122//set GPIO to input mode
 123#define MCP55_MB_SETUP \
 124                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 125                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 126                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 127                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 128
 129#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 130
 131#include "cpu/amd/car/copy_and_run.c"
 132
 133#include "cpu/amd/car/post_cache_as_ram.c"
 134
 135#include "cpu/amd/model_fxx/init_cpus.c"
 136#include "cpu/amd/model_fxx/fidvid.c"
 137
 138#if CONFIG_USE_FALLBACK_IMAGE == 1
 139
 140#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 141#include "northbridge/amd/amdk8/early_ht.c"
 142
 143
 144static void sio_setup(void)
 145{
 146
 147        unsigned value;
 148        uint32_t dword;
 149        uint8_t byte;
 150
 151        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 152        byte |= 0x20;
 153        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 154
 155        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 156        dword |= (1<<0);
 157        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 158
 159
 160}
 161void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 162{
 163        unsigned last_boot_normal_x = last_boot_normal();
 164
 165        /* Is this a cpu only reset? or Is this a secondary cpu? */
 166        if ((cpu_init_detectedx) || (!boot_cpu())) {
 167                if (last_boot_normal_x) {
 168                        goto normal_image;
 169                } else {
 170                        goto fallback_image;
 171                }
 172        }
 173
 174        /* Nothing special needs to be done to find bus 0 */
 175        /* Allow the HT devices to be found */
 176
 177        enumerate_ht_chain();
 178
 179        sio_setup();
 180
 181        /* Setup the mcp55 */
 182        mcp55_enable_rom();
 183
 184        /* Is this a deliberate reset by the bios */
 185        if (bios_reset_detected() && last_boot_normal_x) {
 186                goto normal_image;
 187        }
 188        /* This is the primary cpu how should I boot? */
 189        else if (do_normal_boot()) {
 190                goto normal_image;
 191        }
 192        else {
 193                goto fallback_image;
 194        }
 195 normal_image:
 196        __asm__ volatile ("jmp __normal_image"
 197                : /* outputs */
 198                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 199                );
 200
 201 fallback_image:
 202       ;
 203}
 204#endif
 205
 206void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 207
 208void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 209{
 210
 211#if CONFIG_USE_FALLBACK_IMAGE == 1
 212        failover_process(bist, cpu_init_detectedx);
 213#endif
 214        real_main(bist, cpu_init_detectedx);
 215
 216}
 217
 218//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 219#define RC0 (2<<8)
 220#define RC1 (1<<8)
 221
 222void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 223{
 224       static const uint16_t spd_addr [] = {
 225                       RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 226                       RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 227#if CONFIG_MAX_PHYSICAL_CPUS > 1
 228                       RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 229                       RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 230#endif
 231       };
 232
 233       unsigned bsp_apicid = 0;
 234        int needs_reset;
 235       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 236       char *p ;
 237
 238        if (bist == 0) {
 239               //init_cpus(cpu_init_detectedx);
 240               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 241        }
 242
 243       w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 244        uart_init();
 245        console_init();
 246
 247       /* Halt if there was a built in self test failure */
 248       report_bist_failure(bist);
 249
 250        setup_ms9282_resource_map();
 251
 252       setup_coherent_ht_domain();
 253
 254        wait_all_core0_started();
 255
 256#if CONFIG_LOGICAL_CPUS==1
 257        // It is said that we should start core1 after all core0 launched
 258        start_other_cores();
 259        //wait_all_other_cores_started(bsp_apicid);
 260#endif
 261        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 262
 263       needs_reset = optimize_link_coherent_ht();
 264
 265       needs_reset |= optimize_link_incoherent_ht(sysinfo);
 266
 267        needs_reset |= mcp55_early_setup_x();
 268
 269               if (needs_reset) {
 270                       print_info("ht reset -\r\n");
 271                       soft_reset();
 272               }
 273
 274        //It's the time to set ctrl now;
 275        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 276
 277       enable_smbus();
 278
 279#if 0
 280        int i;
 281        for(i=4;i<8;i++) {
 282                change_i2c_mux(i);
 283                dump_smbus_registers();
 284        }
 285#endif
 286
 287       memreset_setup();
 288
 289       sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 290
 291       post_cache_as_ram();
 292
 293}
 294