1## 2## This file is part of the coreboot project. 3## 4## Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5## 6## This program is free software; you can redistribute it and/or modify 7## it under the terms of the GNU General Public License as published by 8## the Free Software Foundation; either version 2 of the License, or 9## (at your option) any later version. 10## 11## This program is distributed in the hope that it will be useful, 12## but WITHOUT ANY WARRANTY; without even the implied warranty of 13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14## GNU General Public License for more details. 15## 16## You should have received a copy of the GNU General Public License 17## along with this program; if not, write to the Free Software 18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19## 20 21## Based on Config.lb from AMD's DB800 and DBM690T mainboards. 22 23## CONFIG_XIP_ROM_SIZE must be a power of 2. 24default CONFIG_XIP_ROM_SIZE = 64 * 1024 25include /config/nofailovercalculation.lb 26 27## 28## Set all of the defaults for an x86 architecture 29## 30 31arch i386 end 32 33## 34## Build the objects we have code for in this directory. 35## 36 37driver mainboard.o 38 39if CONFIG_GENERATE_PIRQ_TABLE 40 object irq_tables.o 41end 42 43 # compile cache_as_ram.c to auto.inc 44 makerule ./cache_as_ram_auto.inc 45 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" 46 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" 47 action "perl -e 's/.rodata/.rom.data/g' -pi $@" 48 action "perl -e 's/.text/.section .rom.text/g' -pi $@" 49 end 50 51## 52## Build our 16 bit and 32 bit coreboot entry code 53## 54mainboardinit cpu/x86/16bit/entry16.inc 55mainboardinit cpu/x86/32bit/entry32.inc 56ldscript /cpu/x86/16bit/entry16.lds 57ldscript /cpu/x86/32bit/entry32.lds 58 59## 60## Build our reset vector (This is where coreboot is entered) 61## 62if CONFIG_USE_FALLBACK_IMAGE 63 mainboardinit cpu/x86/16bit/reset16.inc 64 ldscript /cpu/x86/16bit/reset16.lds 65else 66 mainboardinit cpu/x86/32bit/reset32.inc 67 ldscript /cpu/x86/32bit/reset32.lds 68end 69 70### Should this be in the northbridge code? 71#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc 72 73## 74## Include an id string (For safe flashing) 75## 76mainboardinit arch/i386/lib/id.inc 77ldscript /arch/i386/lib/id.lds 78 79### 80### This is the early phase of coreboot startup 81### Things are delicate and we test to see if we should 82### failover to another image. 83### 84if CONFIG_USE_FALLBACK_IMAGE 85 ldscript /arch/i386/lib/failover.lds 86# mainboardinit ./failover.inc 87end 88 89### 90### O.k. We aren't just an intermediary anymore! 91### 92 93## 94## Setup RAM 95## 96mainboardinit cpu/x86/fpu_enable.inc 97 98 mainboardinit cpu/amd/model_lx/cache_as_ram.inc 99 mainboardinit ./cache_as_ram_auto.inc 100 101## 102## Include the secondary configuration files 103## 104dir /pc80 105config chip.h 106 107# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED. 108register "sio_gp1x_config" = "0x20" 109 110chip northbridge/amd/lx 111 device pci_domain 0 on 112 device pci 1.0 on end # Northbridge 113 device pci 1.1 on end # Graphics 114 device pci 1.2 on end # AES 115 chip southbridge/amd/cs5536 # Southbridge 116 # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK 117 # SIRQ Mode = Active(Quiet) mode. Save power... 118 # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, 119 # UARTs, etc IRQs. OK 120 register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 121 register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above 122 register "lpc_serirq_mode" = "1" 123 register "enable_gpio_int_route" = "0x0D0C0700" 124 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash 125 register "enable_USBP4_device" = "0" # 0: host, 1:device 126 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) 127 register "com1_enable" = "0" 128 register "com1_address" = "0x3E8" 129 register "com1_irq" = "6" 130 register "com2_enable" = "0" 131 register "com2_address" = "0x2E8" 132 register "com2_irq" = "6" 133 register "unwanted_vpci[0]" = "0" # End of list has a zero 134 device pci 8.0 on end # Slot4 135 device pci 9.0 on end # Slot3 136 device pci a.0 on end # Slot2 137 device pci b.0 on end # Slot1 138 device pci c.0 on end # IT8888 139 device pci e.0 on end # Ethernet 140 device pci f.0 on # ISA bridge 141 chip superio/ite/it8712f 142 device pnp 2e.0 off # Floppy 143 io 0x60 = 0x3f0 144 irq 0x70 = 6 145 drq 0x74 = 2 146 end 147 device pnp 2e.1 on # Com1 148 io 0x60 = 0x3f8 149 irq 0x70 = 4 150 end 151 device pnp 2e.2 on # Com2 152 io 0x60 = 0x2f8 153 irq 0x70 = 3 154 end 155 device pnp 2e.3 on # Parallel port 156 io 0x60 = 0x378 157 irq 0x70 = 7 158 end 159 device pnp 2e.4 on # EC 160 io 0x60 = 0x290 161 io 0x62 = 0x230 162 irq 0x70 = 9 163 end 164 device pnp 2e.5 on # PS/2 keyboard 165 io 0x60 = 0x60 166 io 0x62 = 0x64 167 irq 0x70 = 1 168 end 169 device pnp 2e.6 on # PS/2 mouse 170 irq 0x70 = 12 171 end 172 device pnp 2e.7 on # GPIO 173 io 0x62 = 0x1220 174 # io 0x64 = 0x1200 175 end 176 device pnp 2e.8 off # MIDI 177 io 0x60 = 0x300 178 irq 0x70 = 9 179 end 180 device pnp 2e.9 off # Game port 181 io 0x60 = 0x220 182 end 183 device pnp 2e.a off end # CIR 184 end 185 end 186 device pci f.2 on end # IDE controller 187 device pci f.3 on end # Audio 188 device pci f.4 on end # OHCI 189 device pci f.5 on end # EHCI 190 end 191 end 192 # APIC cluster is late CPU init. 193 device apic_cluster 0 on 194 chip cpu/amd/model_lx 195 device apic 0 on end 196 end 197 end 198end 199