LXR coreboot-v2/src/devices/pcix

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2005 Linux Networx
   5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; version 2 of the License.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21#include <console/console.h>
  22#include <device/device.h>
  23#include <device/pci.h>
  24#include <device/pci_ids.h>
  25#include <device/pcix.h>
  26
  27
  28static void pcix_tune_dev(device_t dev)
  29{
  30        unsigned cap;
  31        unsigned status, orig_cmd, cmd;
  32        unsigned max_read, max_tran;
  33
  34        if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
  35                return;
  36        }
  37        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  38        if (!cap) {
  39                return;
  40        }
  41        printk_debug("%s PCI-X tuning\n", dev_path(dev));
  42        status = pci_read_config32(dev, cap + PCI_X_STATUS);
  43        orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
  44
  45        max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
  46        max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
  47        if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
  48                cmd &= ~PCI_X_CMD_MAX_READ;
  49                cmd |= max_read << 2;
  50        }
  51        if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
  52                cmd &= ~PCI_X_CMD_MAX_SPLIT;
  53                cmd |= max_tran << 4;
  54        }
  55        /* Don't attempt to handle PCI-X errors */
  56        cmd &= ~PCI_X_CMD_DPERR_E;
  57        /* Enable Relaxed Ordering */
  58        cmd |= PCI_X_CMD_ERO;
  59        if (orig_cmd != cmd) {
  60                pci_write_config16(dev, cap + PCI_X_CMD, cmd);
  61        }
  62}
  63
  64unsigned int pcix_scan_bus(struct bus *bus,
  65        unsigned min_devfn, unsigned max_devfn, unsigned int max)
  66{
  67        device_t child;
  68        max = pci_scan_bus(bus, min_devfn, max_devfn, max);
  69        for(child = bus->children; child; child = child->sibling) {
  70                if (    (child->path.pci.devfn < min_devfn) ||
  71                        (child->path.pci.devfn > max_devfn))
  72                {
  73                        continue;
  74                }
  75                pcix_tune_dev(child);
  76        }
  77        return max;
  78}
  79
  80const char *pcix_speed(unsigned sstatus)
  81{
  82        static const char conventional[] = "Conventional PCI";
  83        static const char pcix_66mhz[] = "66MHz PCI-X";
  84        static const char pcix_100mhz[] = "100MHz PCI-X";
  85        static const char pcix_133mhz[] = "133MHz PCI-X";
  86        static const char pcix_266mhz[] = "266MHz PCI-X";
  87        static const char pcix_533mhz[] = "533MHZ PCI-X";
  88        static const char unknown[] = "Unknown";
  89                
  90        const char *result;
  91        result = unknown;
  92        switch(PCI_X_SSTATUS_MFREQ(sstatus)) {
  93        case PCI_X_SSTATUS_CONVENTIONAL_PCI:    
  94                result = conventional; 
  95                break;
  96        case PCI_X_SSTATUS_MODE1_66MHZ:
  97                result = pcix_66mhz;
  98                break;
  99        case PCI_X_SSTATUS_MODE1_100MHZ:
 100                result = pcix_100mhz;
 101                break;
 102                
 103        case PCI_X_SSTATUS_MODE1_133MHZ:
 104                result = pcix_133mhz;
 105                break;
 106                
 107        case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ:
 108        case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ:
 109        case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ:
 110                result = pcix_266mhz;
 111                break;
 112                
 113        case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ:
 114        case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ:
 115        case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ:
 116                result = pcix_533mhz;
 117                break;
 118        }
 119        return result;
 120}
 121
 122unsigned int pcix_scan_bridge(device_t dev, unsigned int max)
 123{
 124        unsigned pos;
 125        unsigned sstatus;
 126
 127        /* Find the PCI-X capability */
 128        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 129        sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
 130
 131        if (PCI_X_SSTATUS_MFREQ(sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
 132                max = do_pci_scan_bridge(dev, max, pci_scan_bus);
 133        } else {
 134                max = do_pci_scan_bridge(dev, max, pcix_scan_bus);
 135        }
 136
 137        /* Print the PCI-X bus speed */
 138        printk_debug("PCI: %02x: %s\n", dev->link[0].secondary, pcix_speed(sstatus));
 139
 140        return max;
 141}
 142
 143
 144/** Default device operations for PCI-X bridges */
 145static struct pci_operations pcix_bus_ops_pci = {
 146        .set_subsystem = 0,
 147};
 148
 149struct device_operations default_pcix_ops_bus = {
 150        .read_resources   = pci_bus_read_resources,
 151        .set_resources    = pci_dev_set_resources,
 152        .enable_resources = pci_bus_enable_resources,
 153        .init             = 0,
 154        .scan_bus         = pcix_scan_bridge,
 155        .enable           = 0,
 156        .reset_bus        = pci_bus_reset,
 157        .ops_pci          = &pcix_bus_ops_pci,
 158};
 159