LXR coreboot-v2/src/boot/hardwaremain.c

   1/*
   2This software and ancillary information (herein called SOFTWARE )
   3called LinuxBIOS          is made available under the terms described
   4here.  The SOFTWARE has been approved for release with associated
   5LA-CC Number 00-34   .  Unless otherwise indicated, this SOFTWARE has
   6been authored by an employee or employees of the University of
   7California, operator of the Los Alamos National Laboratory under
   8Contract No. W-7405-ENG-36 with the U.S. Department of Energy.  The
   9U.S. Government has rights to use, reproduce, and distribute this
  10SOFTWARE.  The public may copy, distribute, prepare derivative works
  11and publicly display this SOFTWARE without charge, provided that this
  12Notice and any statement of authorship are reproduced on all copies.
  13Neither the Government nor the University makes any warranty, express
  14or implied, or assumes any liability or responsibility for the use of
  15this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
  16such modified SOFTWARE should be clearly marked, so as not to confuse
  17it with the version available from LANL.
  18 */
  19/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
  20 * rminnich@lanl.gov
  21 */
  22
  23
  24/*
  25 * C Bootstrap code for the coreboot
  26 */
  27
  28#include <console/console.h>
  29#include <version.h>
  30#include <device/device.h>
  31#include <device/pci.h>
  32#include <delay.h>
  33#include <stdlib.h>
  34#include <part/hard_reset.h>
  35#include <part/init_timer.h>
  36#include <boot/tables.h>
  37#include <boot/elf.h>
  38#include <cbfs.h>
  39#if CONFIG_HAVE_ACPI_RESUME
  40#include <arch/acpi.h>
  41#endif
  42#if CONFIG_WRITE_HIGH_TABLES
  43#include <cbmem.h>
  44#endif
  45
  46/**
  47 * @brief Main function of the RAM part of coreboot.
  48 *
  49 * Coreboot is divided into Pre-RAM part and RAM part. 
  50 * 
  51 * Device Enumeration:
  52 *      In the dev_enumerate() phase, 
  53 */
  54
  55void hardwaremain(int boot_complete);
  56
  57void hardwaremain(int boot_complete)
  58{
  59        struct lb_memory *lb_mem;
  60
  61        post_code(0x80);
  62
  63        /* console_init() MUST PRECEDE ALL printk()! */
  64        console_init();
  65        
  66        post_code(0x39);
  67
  68        printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", 
  69                      coreboot_version, coreboot_extra_version, coreboot_build,
  70                      (boot_complete)?"rebooting":"booting");
  71
  72        post_code(0x40);
  73
  74        /* If we have already booted attempt a hard reboot */
  75        if (boot_complete) {
  76                hard_reset();
  77        }
  78
  79        /* FIXME: Is there a better way to handle this? */
  80        init_timer(); 
  81
  82        /* Find the devices we don't have hard coded knowledge about. */
  83        dev_enumerate();
  84        post_code(0x66);
  85        /* Now compute and assign the bus resources. */
  86        dev_configure();
  87        post_code(0x88);
  88        /* Now actually enable devices on the bus */
  89        dev_enable();
  90        /* And of course initialize devices on the bus */
  91        dev_initialize();
  92        post_code(0x89);
  93
  94#if CONFIG_WRITE_HIGH_TABLES == 1
  95        cbmem_initialize();
  96#endif
  97#if CONFIG_HAVE_ACPI_RESUME == 1
  98        suspend_resume();
  99        post_code(0x8a);
 100#endif
 101
 102        /* Now that we have collected all of our information
 103         * write our configuration tables.
 104         */
 105        lb_mem = write_tables();
 106#if CONFIG_USE_FALLBACK_IMAGE == 1
 107        cbfs_load_payload(lb_mem, "fallback/payload");
 108#else
 109        cbfs_load_payload(lb_mem, "normal/payload");
 110#endif
 111        printk(BIOS_ERR, "Boot failed.\n");
 112}
 113
 114