LXR coreboot-v2/src/northbridge/via/cx700/cx700

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007-2009 coresystems GmbH
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19
  20#include <console/console.h>
  21#include <arch/io.h>
  22#include <device/device.h>
  23#include <device/pci.h>
  24#include <device/pci_ids.h>
  25
  26/* This is the AGP 3.0 "bridge" @ Bus 0 Device 1 Func 0 */
  27
  28static void agp_bridge_init(device_t dev)
  29{
  30
  31        device_t north_dev;
  32        u8 reg8;
  33        north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
  34
  35        pci_write_config8(north_dev, 0xa0, 0x1);        // Enable CPU Direct Access Frame Buffer
  36
  37        pci_write_config8(north_dev, 0xa2, 0x4a);
  38
  39        reg8 = pci_read_config8(north_dev, 0xc0);
  40        reg8 |= 0x1;
  41        pci_write_config8(north_dev, 0xc0, reg8);
  42
  43        /*
  44         * Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer
  45         * We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b
  46         */
  47        north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0);
  48        reg8 = pci_read_config8(north_dev, 0xb5);
  49        reg8 |= 0x3;
  50        pci_write_config8(north_dev, 0xb5, reg8);
  51        pci_write_config8(north_dev, 0x94, 0x20);
  52        pci_write_config8(north_dev, 0x13, 0xd0);
  53
  54        pci_write_config16(dev, 0x4, 0x0007);
  55
  56        pci_write_config8(dev, 0x19, 0x01);
  57        pci_write_config8(dev, 0x1a, 0x01);
  58        pci_write_config8(dev, 0x1c, 0xe0);
  59        pci_write_config8(dev, 0x1d, 0xe0);
  60        pci_write_config16(dev, 0x1e, 0xa220);
  61
  62        pci_write_config16(dev, 0x20, 0xdd00);
  63        pci_write_config16(dev, 0x22, 0xdef0);
  64        pci_write_config16(dev, 0x24, 0xa000);
  65        pci_write_config16(dev, 0x26, 0xbff0);
  66
  67        pci_write_config8(dev, 0x3e, 0x0c);
  68        pci_write_config8(dev, 0x40, 0x8b);
  69        pci_write_config8(dev, 0x41, 0x43);
  70        pci_write_config8(dev, 0x42, 0x62);
  71        pci_write_config8(dev, 0x43, 0x44);
  72        pci_write_config8(dev, 0x44, 0x34);
  73}
  74
  75static void cx700_noop(device_t dev)
  76{
  77}
  78
  79static struct device_operations agp_bridge_operations = {
  80        .read_resources = cx700_noop,
  81        .set_resources = pci_dev_set_resources,
  82        .enable_resources = pci_bus_enable_resources,
  83        .init = agp_bridge_init,
  84        .scan_bus = pci_scan_bridge,
  85};
  86
  87static const struct pci_driver agp_bridge_driver __pci_driver = {
  88        .ops = &agp_bridge_operations,
  89        .vendor = PCI_VENDOR_ID_VIA,
  90        .device = 0xb198,
  91};
  92