LXR coreboot/src/superio/winbond/w83627dhg/superio.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19
  20#include <arch/io.h>
  21#include <device/device.h>
  22#include <device/pnp.h>
  23#include <uart8250.h>
  24#include <pc80/keyboard.h>
  25#include <stdlib.h>
  26#include "chip.h"
  27#include "w83627dhg.h"
  28
  29static void pnp_enter_ext_func_mode(device_t dev)
  30{
  31        outb(0x87, dev->path.pnp.port);
  32        outb(0x87, dev->path.pnp.port);
  33}
  34
  35static void pnp_exit_ext_func_mode(device_t dev)
  36{
  37        outb(0xaa, dev->path.pnp.port);
  38}
  39
  40static void w83627dhg_init(device_t dev)
  41{
  42        struct superio_winbond_w83627dhg_config *conf = dev->chip_info;
  43
  44        if (!dev->enabled)
  45                return;
  46
  47        switch(dev->path.pnp.device) {
  48        case W83627DHG_KBC:
  49                pc_keyboard_init(&conf->keyboard);
  50                break;
  51        }
  52}
  53
  54static void w83627dhg_pnp_set_resources(device_t dev)
  55{
  56        pnp_enter_ext_func_mode(dev);
  57        pnp_set_resources(dev);
  58        pnp_exit_ext_func_mode(dev);
  59}
  60
  61static void w83627dhg_pnp_enable_resources(device_t dev)
  62{
  63        pnp_enter_ext_func_mode(dev);
  64        pnp_enable_resources(dev);
  65        pnp_exit_ext_func_mode(dev);
  66}
  67
  68static void w83627dhg_pnp_enable(device_t dev)
  69{
  70        pnp_enter_ext_func_mode(dev);
  71        pnp_set_logical_device(dev);
  72        pnp_set_enable(dev, !!dev->enabled);
  73        pnp_exit_ext_func_mode(dev);
  74}
  75
  76static struct device_operations ops = {
  77        .read_resources   = pnp_read_resources,
  78        .set_resources    = w83627dhg_pnp_set_resources,
  79        .enable_resources = w83627dhg_pnp_enable_resources,
  80        .enable           = w83627dhg_pnp_enable,
  81        .init             = w83627dhg_init,
  82};
  83
  84static struct pnp_info pnp_dev_info[] = {
  85        { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  86        { &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  87        { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
  88        { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
  89        { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
  90        /* the next line makes coreboot hang in pnp_enable_devices() */
  91        /* { &ops, W83627DHG_SPI, PNP_IO1, { 0x7f8, 0 }, }, */
  92        { &ops, W83627DHG_GPIO6, },
  93        { &ops, W83627DHG_WDTO_PLED, },
  94        { &ops, W83627DHG_GPIO2, },
  95        { &ops, W83627DHG_GPIO3, },
  96        { &ops, W83627DHG_GPIO4, },
  97        { &ops, W83627DHG_GPIO5, },
  98        { &ops, W83627DHG_ACPI, PNP_IRQ0, },
  99        { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
 100        { &ops, W83627DHG_PECI_SST, },
 101};
 102
 103static void enable_dev(struct device *dev)
 104{
 105        pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 106}
 107
 108struct chip_operations superio_winbond_w83627dhg_ops = {
 109        CHIP_NAME("Winbond W83627DHG Super I/O")
 110        .enable_dev = enable_dev,
 111};
 112