LXR coreboot/src/superio/fintek/f71863fg/superio.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21#include <arch/io.h>
  22#include <device/device.h>
  23#include <device/pnp.h>
  24#include <console/console.h>
  25#include <stdlib.h>
  26#include <uart8250.h>
  27#include "chip.h"
  28#include "f71863fg.h"
  29
  30static void pnp_enter_conf_state(device_t dev)
  31{
  32        outb(0x87, dev->path.pnp.port);
  33        outb(0x87, dev->path.pnp.port);
  34}
  35
  36static void pnp_exit_conf_state(device_t dev)
  37{
  38        outb(0xaa, dev->path.pnp.port);
  39}
  40
  41static void f71863fg_init(device_t dev)
  42{
  43        struct superio_fintek_f71863fg_config *conf = dev->chip_info;
  44        struct resource *res0;
  45
  46        if (!dev->enabled)
  47                return;
  48
  49        switch(dev->path.pnp.device) {
  50        /* TODO: Might potentially need code for HWM or FDC etc. */
  51        case F71863FG_KBC:
  52                res0 = find_resource(dev, PNP_IDX_IO0);
  53                pc_keyboard_init(&conf->keyboard);
  54                break;
  55        }
  56}
  57
  58static void f71863fg_pnp_set_resources(device_t dev)
  59{
  60        pnp_enter_conf_state(dev);
  61        pnp_set_resources(dev);
  62        pnp_exit_conf_state(dev);
  63}
  64
  65static void f71863fg_pnp_enable_resources(device_t dev)
  66{
  67        pnp_enter_conf_state(dev);
  68        pnp_enable_resources(dev);
  69        pnp_exit_conf_state(dev);
  70}
  71
  72static void f71863fg_pnp_enable(device_t dev)
  73{
  74        pnp_enter_conf_state(dev);
  75        pnp_set_logical_device(dev);
  76        pnp_set_enable(dev, !!dev->enabled);
  77        pnp_exit_conf_state(dev);
  78}
  79
  80static struct device_operations ops = {
  81        .read_resources   = pnp_read_resources,
  82        .set_resources    = f71863fg_pnp_set_resources,
  83        .enable_resources = f71863fg_pnp_enable_resources,
  84        .enable           = f71863fg_pnp_enable,
  85        .init             = f71863fg_init,
  86};
  87
  88static struct pnp_info pnp_dev_info[] = {
  89        /* TODO: Some of the 0x07f8 etc. values may not be correct. */
  90        { &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  91        { &ops, F71863FG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
  92        { &ops, F71863FG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
  93        { &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  94        { &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
  95        { &ops, F71863FG_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
  96        { &ops, F71863FG_GPIO, },
  97        { &ops, F71863FG_VID,  PNP_IO0, {0x07f8, 0}, },
  98        { &ops, F71863FG_SPI, },
  99        { &ops, F71863FG_PME, },
 100};
 101
 102static void enable_dev(device_t dev)
 103{
 104        pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 105}
 106
 107struct chip_operations superio_fintek_f71863fg_ops = {
 108        CHIP_NAME("Fintek F71863FG Super I/O")
 109        .enable_dev = enable_dev
 110};
 111