LXR coreboot/src/southbridge/via/vt8237r/lpc.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
   5 * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; version 2 of the License.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21/* Inspiration from other VIA SB code. */
  22
  23#include <arch/io.h>
  24#include <console/console.h>
  25#include <device/device.h>
  26#include <device/pci.h>
  27#include <device/pci_ids.h>
  28#include <pc80/mc146818rtc.h>
  29#include <arch/ioapic.h>
  30#include <cpu/x86/lapic.h>
  31#include <cpu/cpu.h>
  32#include <pc80/keyboard.h>
  33#include <pc80/i8259.h>
  34#include <stdlib.h>
  35#include "vt8237r.h"
  36#include "chip.h"
  37
  38static void southbridge_init_common(struct device *dev);
  39
  40#if CONFIG_EPIA_VT8237R_INIT
  41                   /* Interrupts for  INT# A   B   C   D */
  42static const unsigned char pciIrqs[4]  = { 10, 11, 12, 0};
  43
  44            /* Interrupt Assignments for Pins   1   2   3   4  */
  45static const unsigned char sataPins[4] =     { 'A','B','C','D'};
  46static const unsigned char vgaPins[4] =      { 'A','B','C','D'};
  47static const unsigned char usbPins[4] =      { 'A','B','C','D'};
  48static const unsigned char enetPins[4] =     { 'A','B','C','D'};
  49static const unsigned char vt8237Pins[4] =   { 'A','B','C','D'};
  50static const unsigned char slotPins[4] =     { 'C','D','A','B'};
  51static const unsigned char riserPins[4] =    { 'D','C','B','A'};
  52
  53static unsigned char *pin_to_irq(const unsigned char *pin)
  54{
  55        static unsigned char Irqs[4];
  56        int i;
  57        for (i = 0 ; i < 4 ; i++)
  58                Irqs[i] = pciIrqs[ pin[i] - 'A' ];
  59
  60        return Irqs;
  61}
  62#endif
  63
  64/** Set up PCI IRQ routing, route everything through APIC. */
  65static void pci_routing_fixup(struct device *dev)
  66{
  67#if CONFIG_EPIA_VT8237R_INIT
  68        device_t pdev;
  69#endif
  70
  71        /* PCI PNP Interrupt Routing INTE/F - disable */
  72        pci_write_config8(dev, 0x44, 0x00);
  73
  74        /* PCI PNP Interrupt Routing INTG/H - disable */
  75        pci_write_config8(dev, 0x45, 0x00);
  76
  77        /* Gate Interrupts until RAM Writes are flushed */
  78        pci_write_config8(dev, 0x49, 0x20);
  79
  80#if CONFIG_EPIA_VT8237R_INIT
  81
  82        /* Share INTE-INTH with INTA-INTD as per stock BIOS. */
  83        pci_write_config8(dev, 0x46, 0x00);
  84
  85        /* setup PCI IRQ routing (For PCI Slot)*/
  86        pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
  87        pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
  88        pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
  89
  90        /* PCI Routing Fixup */
  91
  92        //Setup MiniPCI Slot
  93        pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
  94
  95        // Via 2 slot riser card 2nd slot
  96        pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
  97
  98        //Setup USB
  99        pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
 100
 101        //Setup VT8237R Sound
 102        pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins));
 103
 104        //Setup Ethernet
 105        pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
 106
 107        //Setup VGA
 108        pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
 109
 110        /* APIC Routing Fixup */
 111
 112        // Setup SATA
 113        pdev = dev_find_device(PCI_VENDOR_ID_VIA,
 114                                PCI_DEVICE_ID_VIA_VT6420_SATA, 0);
 115        pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02);
 116        pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins));
 117
 118
 119        // Setup PATA Override
 120        pdev = dev_find_device(PCI_VENDOR_ID_VIA,
 121                                PCI_DEVICE_ID_VIA_82C586_1, 0);
 122        pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01);
 123        pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF);
 124
 125#else
 126        /* Route INTE-INTH through registers above, no map to INTA-INTD. */
 127        pci_write_config8(dev, 0x46, 0x10);
 128
 129        /* PCI Interrupt Polarity */
 130        pci_write_config8(dev, 0x54, 0x00);
 131
 132        /* PCI INTA# Routing */
 133        pci_write_config8(dev, 0x55, 0x00);
 134
 135        /* PCI INTB#/C# Routing */
 136        pci_write_config8(dev, 0x56, 0x00);
 137
 138        /* PCI INTD# Routing */
 139        pci_write_config8(dev, 0x57, 0x00);
 140#endif
 141}
 142
 143
 144
 145/**
 146 * Set up the power management capabilities directly into ACPI mode.
 147 * This avoids having to handle any System Management Interrupts (SMIs).
 148 */
 149
 150extern u8 acpi_slp_type;
 151
 152
 153static void setup_pm(device_t dev)
 154{
 155        u16 tmp;
 156        /* Debounce LID and PWRBTN# Inputs for 16ms. */
 157        pci_write_config8(dev, 0x80, 0x20);
 158
 159        /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
 160        pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
 161
 162        /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
 163        pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
 164
 165#if CONFIG_EPIA_VT8237R_INIT
 166        /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
 167        pci_write_config16(dev, 0x84, 0x3052);
 168#else
 169        /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
 170        pci_write_config16(dev, 0x84, 0x30b2);
 171
 172#endif
 173        /* SMI output level to low, 7.5us throttle clock */
 174        pci_write_config8(dev, 0x8d, 0x18);
 175
 176        /* GP Timer Control 1s */
 177        pci_write_config8(dev, 0x93, 0x88);
 178
 179        /*
 180         * 7 = SMBus clock from RTC 32.768KHz
 181         * 5 = Internal PLL reset from susp disabled
 182         * 2 = GPO2 is SUSA#
 183         */
 184        pci_write_config8(dev, 0x94, 0xa0);
 185
 186        /*
 187         * 7 = stp to sust delay 1msec
 188         * 6 = SUSST# Deasserted Before PWRGD for STD
 189         * 5 = Keyboard/Mouse Swap
 190         * 4 = PWRGOOD reset on VT8237A/S
 191         * 3 = GPO26/GPO27 is GPO
 192         * 2 = Disable Alert on Lan
 193         * 1 = SUSCLK/GPO4
 194         * 0 = USB Wakeup
 195         */
 196
 197#if CONFIG_EPIA_VT8237R_INIT
 198        pci_write_config8(dev, 0x95, 0xc2);
 199#else
 200        pci_write_config8(dev, 0x95, 0xcc);
 201#endif
 202
 203        /* Disable GP3 timer. */
 204        pci_write_config8(dev, 0x98, 0);
 205
 206        /* Enable ACPI accessm RTC signal gated with PSON. */
 207        pci_write_config8(dev, 0x81, 0x84);
 208
 209        /* Clear status events. */
 210        outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00);
 211        outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20);
 212        outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28);
 213        outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30);
 214
 215        /* Disable SCI on GPIO. */
 216        outw(0x0, VT8237R_ACPI_IO_BASE + 0x22);
 217
 218        /* Disable SMI on GPIO. */
 219        outw(0x0, VT8237R_ACPI_IO_BASE + 0x24);
 220
 221        /* Disable all global enable SMIs, except SW SMI */
 222        outw(0x40, VT8237R_ACPI_IO_BASE + 0x2a);
 223
 224        /* Primary activity SMI disable. */
 225        outl(0x0, VT8237R_ACPI_IO_BASE + 0x34);
 226
 227        /* GP timer reload on none. */
 228        outl(0x0, VT8237R_ACPI_IO_BASE + 0x38);
 229
 230        /* Disable extended IO traps. */
 231        outb(0x0, VT8237R_ACPI_IO_BASE + 0x42);
 232
 233        /* SCI is generated for RTC/pwrBtn/slpBtn. */
 234        tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
 235#if CONFIG_HAVE_ACPI_RESUME == 1
 236        acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
 237        printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
 238#endif
 239
 240        /* All SMI on, both IDE buses ON, PSON rising edge. */
 241        outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c);
 242
 243        /* clear sleep */
 244        tmp &= ~(7 << 10);
 245        tmp |= 1;
 246        outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
 247}
 248
 249static void vt8237r_init(struct device *dev)
 250{
 251        u8 enables;
 252
 253#if CONFIG_EPIA_VT8237R_INIT
 254        printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
 255        /*
 256         * TODO: Looks like stock BIOS can do this but causes a hang
 257         * Enable SATA LED, disable special CPU Frequency Change -
 258         * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
 259         * Setup to match EPIA default
 260         * PCS0# on Pin U1
 261         */
 262        enables = pci_read_config8(dev, 0xe5);
 263        enables |= 0x23;
 264        pci_write_config8(dev, 0xe5, enables);
 265
 266        /*
 267         * Enable Flash Write Access.
 268         * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
 269         */
 270        enables = pci_read_config8(dev, 0xe4);
 271        enables |= 0x2B;
 272        pci_write_config8(dev, 0xe4, enables);
 273
 274        /* Enables Extra RTC Ports */
 275        enables = pci_read_config8(dev, 0x4E);
 276        enables |= 0x80;
 277        pci_write_config8(dev, 0x4E, enables);
 278
 279#else
 280        printk(BIOS_SPEW, "Entering vt8237r_init.\n");
 281        /*
 282         * Enable SATA LED, disable special CPU Frequency Change -
 283         * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
 284         */
 285        pci_write_config8(dev, 0xe5, 0x09);
 286
 287        /* REQ5 as PCI request input - should be together with INTE-INTH. */
 288        pci_write_config8(dev, 0xe4, 0x4);
 289#endif
 290
 291        /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
 292        enables = pci_read_config8(dev, 0x4f);
 293        enables |= 0x08;
 294        pci_write_config8(dev, 0x4f, enables);
 295
 296#if CONFIG_EPIA_VT8237R_INIT
 297        /*
 298         * Set Read Pass Write Control Enable
 299         */
 300        pci_write_config8(dev, 0x48, 0x0c);
 301#else
 302        
 303  #if CONFIG_SOUTHBRIDGE_VIA_K8T800
 304        /* It seems that when we pair with the K8T800, we need to disable
 305         * the A2 mask
 306         */
 307        pci_write_config8(dev, 0x48, 0x0c);
 308  #else
 309        /*
 310         * Set Read Pass Write Control Enable
 311         * (force A2 from APIC FSB to low).
 312         */
 313        pci_write_config8(dev, 0x48, 0x8c);
 314  #endif
 315        
 316#endif
 317
 318        southbridge_init_common(dev);
 319
 320#if !CONFIG_EPIA_VT8237R_INIT
 321        /* FIXME: Intel needs more bit set for C2/C3. */
 322
 323        /*
 324         * Allow SLP# signal to assert LDTSTOP_L.
 325         * Will work for C3 and for FID/VID change.
 326         */
 327        outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
 328#endif
 329
 330        printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 331        printk(BIOS_SPEW, "And taking a dump:\n");
 332        dump_south(dev);        
 333}
 334
 335static void vt8237a_init(struct device *dev)
 336{
 337        /*
 338         * FIXME: This is based on vt8237s_init() and the values the AMI
 339         *        BIOS on my M2V wrote to these registers (by loking
 340         *        at lspci -nxxx output).
 341         *        Works for me.
 342         */
 343        u32 tmp;
 344
 345        /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
 346        tmp = pci_read_config8(dev, 0x4f);
 347        tmp |= 0x08;
 348        pci_write_config8(dev, 0x4f, tmp);
 349
 350        /*
 351         * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
 352         * bit5: usb power control lines as gpio
 353         */
 354        pci_write_config8(dev, 0xe4, 0x24);
 355        /*
 356         * Enable APIC wakeup from INTH
 357         * Enable SATA LED, disable special CPU Frequency Change -
 358         * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
 359         */
 360        pci_write_config8(dev, 0xe5, 0x69);
 361
 362        /* Reduce further the STPCLK/LDTSTP signal to 5us. */
 363        pci_write_config8(dev, 0xec, 0x4);
 364
 365        /* Host Bus Power Management Control, maybe not needed */
 366        pci_write_config8(dev, 0x8c, 0x5);
 367
 368        /* Enable HPET at VT8237R_HPET_ADDR. */
 369        pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
 370
 371        southbridge_init_common(dev);
 372
 373        /* Share INTE-INTH with INTA-INTD for simplicity */
 374        pci_write_config8(dev, 0x46, 0x00);
 375
 376        /* FIXME: Intel needs more bit set for C2/C3. */
 377
 378        /*
 379         * Allow SLP# signal to assert LDTSTOP_L.
 380         * Will work for C3 and for FID/VID change.
 381         */
 382        outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
 383
 384        dump_south(dev);
 385}
 386
 387static void vt8237s_init(struct device *dev)
 388{
 389        u32 tmp;
 390
 391        /* Put SPI base VT8237S_SPI_MEM_BASE. */
 392        tmp = pci_read_config32(dev, 0xbc);
 393        pci_write_config32(dev, 0xbc,
 394                           (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
 395
 396        /*
 397         * REQ5 as PCI request input - should be together with INTE-INTH.
 398         */
 399        pci_write_config8(dev, 0xe4, 0x04);
 400
 401        /* Reduce further the STPCLK/LDTSTP signal to 5us. */
 402        pci_write_config8(dev, 0xec, 0x4);
 403
 404        /* Host Bus Power Management Control, maybe not needed */
 405        pci_write_config8(dev, 0x8c, 0x5);
 406
 407        /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */
 408        pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
 409
 410        southbridge_init_common(dev);
 411
 412        /* FIXME: Intel needs more bit set for C2/C3. */
 413
 414        /*
 415         * Allow SLP# signal to assert LDTSTOP_L.
 416         * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
 417         */
 418        outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
 419
 420        dump_south(dev);
 421}
 422
 423static void vt8237_common_init(struct device *dev)
 424{
 425        u8 enables, byte;
 426
 427        /* Enable addr/data stepping. */
 428        byte = pci_read_config8(dev, PCI_COMMAND);
 429        byte |= PCI_COMMAND_WAIT;
 430        pci_write_config8(dev, PCI_COMMAND, byte);
 431
 432/* EPIA-N(L) Uses CN400 for BIOS Access */
 433#if !CONFIG_EPIA_VT8237R_INIT
 434        /* Enable the internal I/O decode. */
 435        enables = pci_read_config8(dev, 0x6C);
 436        enables |= 0x80;
 437        pci_write_config8(dev, 0x6C, enables);
 438
 439        /*
 440         * ROM decode
 441         * bit range
 442         *   7 000E0000h-000EFFFFh
 443         *   6 FFF00000h-FFF7FFFFh
 444         *   5 FFE80000h-FFEFFFFFh
 445         *   4 FFE00000h-FFE7FFFFh
 446         *   3 FFD80000h-FFDFFFFFh
 447         *   2 FFD00000h-FFD7FFFFh
 448         *   1 FFC80000h-FFCFFFFFh
 449         *   0 FFC00000h-FFC7FFFFh
 450         * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
 451         */
 452        pci_write_config8(dev, 0x41, 0x7f);
 453#endif
 454
 455        /*
 456         * Set bit 6 of 0x40 (I/O recovery time).
 457         * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
 458         * that PCI interrupts can be properly marked as level triggered.
 459         */
 460        enables = pci_read_config8(dev, 0x40);
 461        enables |= 0x44;
 462        pci_write_config8(dev, 0x40, enables);
 463
 464        /* Line buffer control */
 465        enables = pci_read_config8(dev, 0x42);
 466        enables |= 0xf8;
 467        pci_write_config8(dev, 0x42, enables);
 468
 469        /* Delay transaction control */
 470        pci_write_config8(dev, 0x43, 0xb);
 471
 472#if CONFIG_EPIA_VT8237R_INIT
 473        /* I/O recovery time, default IDE routing */
 474        pci_write_config8(dev, 0x4c, 0x04);
 475
 476        /* ROM memory cycles go to LPC. */
 477        pci_write_config8(dev, 0x59, 0x80);
 478
 479        /*
 480         * Bit | Meaning
 481         * -------------
 482         *   3 | Bypass APIC De-Assert Message (1=Enable)
 483         *   2 | APIC HyperTransport Mode (1=Enable)
 484         *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
 485         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
 486         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
 487         */
 488        pci_write_config8(dev, 0x5b, 0x9);
 489
 490        /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/
 491        pci_write_config8(dev, 0x58, 0x42);
 492
 493        /* Enable serial IRQ, 6PCI clocks. */
 494        pci_write_config8(dev, 0x52, 0x9);
 495#else
 496        /* I/O recovery time, default IDE routing */
 497        pci_write_config8(dev, 0x4c, 0x44);
 498
 499        /* ROM memory cycles go to LPC. */
 500        pci_write_config8(dev, 0x59, 0x80);
 501
 502        /*
 503         * Bit | Meaning
 504         * -------------
 505         *   3 | Bypass APIC De-Assert Message (1=Enable)
 506         *   2 | APIC HyperTransport Mode (1=Enable)
 507         *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
 508         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
 509         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
 510         */
 511        pci_write_config8(dev, 0x5b, 0xb);
 512
 513        /* Set 0x58 to 0x43 APIC and RTC. */
 514        pci_write_config8(dev, 0x58, 0x43);
 515
 516        /* Enable serial IRQ, 6PCI clocks. */
 517        pci_write_config8(dev, 0x52, 0x9);
 518#endif
 519#if CONFIG_HAVE_SMI_HANDLER
 520        smm_lock();
 521#endif
 522
 523        /* Power management setup */
 524        setup_pm(dev);
 525
 526        /* Start the RTC. */
 527        rtc_init(0);
 528}
 529
 530static void vt8237r_read_resources(device_t dev)
 531{
 532        struct resource *res;
 533
 534        pci_dev_read_resources(dev);
 535
 536        /* Fixed ACPI Base IO Base*/
 537        res = new_resource(dev, 0x88);
 538        res->base = VT8237R_ACPI_IO_BASE;
 539        res->size = 128;
 540        res->limit = 0xffffUL;
 541        res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 542                     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 543
 544        /* Fixed EISA ECLR I/O Regs     */
 545        res = new_resource(dev, 3);
 546        res->base = 0x4d0;
 547        res->size = 2;
 548        res->limit = 0xffffUL;
 549        res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 550                     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 551
 552        /* Fixed System Management Bus I/O Resource */
 553        res = new_resource(dev, 0xD0);
 554        res->base = VT8237R_SMBUS_IO_BASE;
 555        res->size = 16;
 556        res->limit = 0xffffUL;
 557        res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 558                     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 559
 560        /* Fixed APIC resource */
 561        res = new_resource(dev, 0x44);
 562        res->base = IO_APIC_ADDR;
 563        res->size = 256;
 564        res->limit = 0xffffffffUL;
 565        res->align = 8;
 566        res->gran = 8;
 567        res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 568                     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 569
 570        /* Fixed flashrom resource */
 571        res = new_resource(dev, 4);
 572        res->base = 0xff000000UL;
 573        res->size = 0x01000000UL; /* 16MB */
 574        res->limit = 0xffffffffUL;
 575        res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
 576                     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 577
 578        res = new_resource(dev, 1);
 579        res->base = 0x0UL;
 580        res->size = 0x1000UL;
 581        res->limit = 0xffffUL;
 582        res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 583}
 584
 585static void init_keyboard(struct device *dev)
 586{
 587        u8 regval = pci_read_config8(dev, 0x51);
 588        if (regval & 0x1)
 589                pc_keyboard_init(0);
 590}
 591
 592static void southbridge_init_common(struct device *dev)
 593{
 594        vt8237_common_init(dev);
 595        pci_routing_fixup(dev);
 596        setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
 597        setup_i8259();
 598        init_keyboard(dev);
 599}
 600
 601static const struct device_operations vt8237r_lpc_ops_s = {
 602        .read_resources         = vt8237r_read_resources,
 603        .set_resources          = pci_dev_set_resources,
 604        .enable_resources       = pci_dev_enable_resources,
 605        .init                   = vt8237s_init,
 606        .scan_bus               = scan_static_bus,
 607};
 608
 609static const struct device_operations vt8237r_lpc_ops_r = {
 610        .read_resources         = vt8237r_read_resources,
 611        .set_resources          = pci_dev_set_resources,
 612        .enable_resources       = pci_dev_enable_resources,
 613        .init                   = vt8237r_init,
 614        .scan_bus               = scan_static_bus,
 615};
 616
 617static const struct device_operations vt8237r_lpc_ops_a = {
 618        .read_resources         = vt8237r_read_resources,
 619        .set_resources          = pci_dev_set_resources,
 620        .enable_resources       = pci_dev_enable_resources,
 621        .init                   = vt8237a_init,
 622        .scan_bus               = scan_static_bus,
 623};
 624
 625static const struct pci_driver lpc_driver_r __pci_driver = {
 626        .ops    = &vt8237r_lpc_ops_r,
 627        .vendor = PCI_VENDOR_ID_VIA,
 628        .device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
 629};
 630
 631static const struct pci_driver lpc_driver_a __pci_driver = {
 632        .ops    = &vt8237r_lpc_ops_a,
 633        .vendor = PCI_VENDOR_ID_VIA,
 634        .device = PCI_DEVICE_ID_VIA_VT8237A_LPC,
 635};
 636
 637static const struct pci_driver lpc_driver_s __pci_driver = {
 638        .ops    = &vt8237r_lpc_ops_s,
 639        .vendor = PCI_VENDOR_ID_VIA,
 640        .device = PCI_DEVICE_ID_VIA_VT8237S_LPC,
 641};
 642