LXR coreboot/src/southbridge/intel/i82371eb/i82371eb.h

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
  22#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
  23
  24#if !defined(__ASSEMBLER__)
  25#if !defined(__PRE_RAM__)
  26#if !defined(__ACPI__) /* dsdt include */
  27
  28#include <arch/io.h>
  29#include <device/device.h>
  30#include "chip.h"
  31
  32void i82371eb_enable(device_t dev);
  33void i82371eb_hard_reset(void);
  34
  35#endif
  36#endif
  37#endif
  38
  39#if defined(__PRE_RAM__) && !defined(__ROMCC__)
  40void enable_smbus(void);
  41int smbus_read_byte(u8 device, u8 address);
  42void enable_pm(void);
  43#endif
  44
  45/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
  46 * 'reg' variable, otherwise it clears those bits.
  47 *
  48 * Examples:
  49 * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5));
  50 * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR));
  51 */
  52/* TODO: Move into some global header file? */
  53#define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits)))
  54
  55#define XBCS            0x4e    /* X-Bus chip select register */
  56#define GENCFG          0xb0    /* General configuration register */
  57#define RC              0xcf9   /* Reset control register */
  58
  59/* IDE */
  60#define IDETIM_PRI      0x40    /* IDE timing register, primary channel */
  61#define IDETIM_SEC      0x42    /* IDE timing register, secondary channel */
  62#define UDMACTL         0x48    /* Ultra DMA/33 control register */
  63#define UDMATIM         0x4a    /* Ultra DMA/33 timing register */
  64
  65/* SMBus */
  66#define SMBBA           0x90    /* SMBus base address */
  67#define   SMBUS_IO_BASE 0x0f00
  68#define SMBHSTCFG       0xd2    /* SMBus host configuration */
  69
  70/* Power management (ACPI) */
  71#define PMSTS           0x00    /* Power Management Status */
  72#define PMEN            0x02    /* Power Management Resume Enable */
  73#define   PWRBTN_EN     (1<<8)
  74#define   GBL_EN        (1<<5)
  75#define PMCNTRL         0x04    /* Power Management Control */
  76#define   SUS_EN        (1<<13) /* S0-S5 trigger */
  77#define   SUS_TYP_MSK   (7<<10)
  78#define   SUS_TYP_S0    (5<<10)
  79#define   SUS_TYP_S1    (4<<10)
  80#define   SUS_TYP_S2    (3<<10)
  81//#define   SUS_TYP_S2>---(2<<10)
  82#define   SUS_TYP_S3    (1<<10)
  83#define   SUS_TYP_S5    (0<<10)
  84#define   SCI_EN        (1<<0)
  85#define PMTMR           0x08    /* Power Management Timer */
  86#define GPSTS           0x0c    /* General Purpose Status */
  87#define GPEN            0x0e    /* General Purpose Enable */
  88#define   THRM_EN       (1<<0)
  89#define PCNTRL          0x10    /* Processor control */
  90#define GLBSTS          0x18    /* Global Status */
  91#define   IRQ_RSM_STS   (1<<11)
  92#define   EXTSMI_STS    (1<<10)
  93#define   GSTBY_STS     (1<<8)
  94#define   GP_STS        (1<<7)
  95#define   BM1_STS       (1<<6)
  96#define   APM_STS       (1<<5)
  97#define   DEV_STS       (1<<4)
  98#define   BIOS_EN       (1<<1)  /* GBL_RLS write triggers SMI */
  99#define   LEGACY_USB_EN (1<<0)  /* Keyboard controller access triggers SMI */
 100#define DEVSTS          0x1c    /* Device Status */
 101#define GLBEN           0x20    /* Global Enable */
 102#define   EXTSMI_EN     (1<<10) /* EXTSMI# signal triggers SMI */
 103#define   GSTBY_EN      (1<<8)
 104#define   BM_TRP_EN     (1<<1)
 105#define   BIOS_EN       (1<<1)  /* GBL_RLS write triggers SMI */
 106#define   LEGACY_USB_EN (1<<0)  /* Keyboard controller access triggers SMI */
 107#define GLBCTL          0x28    /* Global Control */
 108#define   EOS           (1<<16) /* End of SMI */
 109#define   SMI_EN        (1<<0)  /* SMI enable */
 110#define DEVCTL          0x2c    /* Device Control */
 111#define   TRP_EN_DEV12  (1<<24) /* SMI on dev12 trap */
 112#define GPO0            0x34
 113#define GPO1            0x35
 114#define GPO2            0x36
 115#define GPO3            0x37
 116
 117#define PMBA            0x40    /* Power management base address */
 118#define   DEFAULT_PMBASE        0xe400
 119#define   PM_IO_BASE DEFAULT_PMBASE
 120#define PMREGMISC       0x80    /* Miscellaneous power management */
 121
 122/* Bit definitions */
 123#define EXT_BIOS_ENABLE_1MB     (1 << 9)  /* 1-Meg Extended BIOS Enable */
 124#define EXT_BIOS_ENABLE         (1 << 7)  /* Extended BIOS Enable */
 125#define LOWER_BIOS_ENABLE       (1 << 6)  /* Lower BIOS Enable */
 126#define WRITE_PROTECT_ENABLE    (1 << 2)  /* Write Protect Enable */
 127#define SRST                    (1 << 1)  /* System Reset */
 128#define RCPU                    (1 << 2)  /* Reset CPU */
 129#define SMB_HST_EN              (1 << 0)  /* Host Interface Enable */
 130#define IDE_DECODE_ENABLE       (1 << 15) /* IDE Decode Enable */
 131#define DTE0                    (1 << 3)  /* DMA Timing Enable Only, drive 0 */
 132#define DTE1                    (1 << 7)  /* DMA Timing Enable Only, drive 1 */
 133#define PSDE0                   (1 << 0)  /* Primary Drive 0 UDMA/33 */
 134#define PSDE1                   (1 << 1)  /* Primary Drive 1 UDMA/33 */
 135#define SSDE0                   (1 << 2)  /* Secondary Drive 0 UDMA/33 */
 136#define SSDE1                   (1 << 3)  /* Secondary Drive 1 UDMA/33 */
 137#define ISA                     (1 << 0)  /* Select ISA */
 138#define EIO                     (0 << 0)  /* Select EIO */
 139#define PMIOSE                  (1 << 0)  /* PM I/O Space Enable */
 140
 141#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
 142