LXR coreboot/src/southbridge/intel/i82371eb/early

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21#include <stdint.h>
  22#include <arch/io.h>
  23#include <arch/romcc_io.h>
  24#include <device/pci_def.h>
  25#include <device/pci_ids.h>
  26#include <console/console.h>
  27#include "i82371eb.h"
  28
  29void enable_pm(void)
  30{
  31        device_t dev;
  32        u8 reg8;
  33        u16 reg16;
  34
  35        /* Get the SMBus/PM device of the 82371AB/EB/MB. */
  36        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
  37                                PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
  38
  39        /* Set the PM I/O base. */
  40        pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
  41
  42        /* Enable access to the PM I/O space. */
  43        reg16 = pci_read_config16(dev, PCI_COMMAND);
  44        reg16 |= PCI_COMMAND_IO;
  45        pci_write_config16(dev, PCI_COMMAND, reg16);
  46
  47        /* PM I/O Space Enable (PMIOSE). */
  48        reg8 = pci_read_config8(dev, PMREGMISC);
  49        reg8 |= PMIOSE;
  50        pci_write_config8(dev, PMREGMISC, reg8);
  51}
  52