LXR coreboot/src/southbridge/amd/sb800/sb800.h

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19
  20#ifndef SB800_H
  21#define SB800_H
  22
  23#include <device/pci_ids.h>
  24#include "chip.h"
  25
  26/* Power management index/data registers */
  27#define BIOSRAM_INDEX   0xcd4
  28#define BIOSRAM_DATA    0xcd5
  29#define PM_INDEX        0xcd6
  30#define PM_DATA         0xcd7
  31#define PM2_INDEX       0xcd0
  32#define PM2_DATA        0xcd1
  33
  34#define SB800_ACPI_IO_BASE 0x800
  35
  36#define ACPI_PM_EVT_BLK         (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */
  37#define ACPI_PM1_CNT_BLK        (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */
  38#define ACPI_PMA_CNT_BLK        (SB800_ACPI_IO_BASE + 0x0F) /* 1 byte */
  39#define ACPI_PM_TMR_BLK         (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */
  40#define ACPI_GPE0_BLK           (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */
  41#define ACPI_CPU_CONTROL        (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */
  42
  43void pm_iowrite(u8 reg, u8 value);
  44u8 pm_ioread(u8 reg);
  45void pm2_iowrite(u8 reg, u8 value);
  46u8 pm2_ioread(u8 reg);
  47void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
  48
  49#define REV_SB800_A11   0x11
  50#define REV_SB800_A12   0x12
  51
  52
  53#ifdef __PRE_RAM__
  54void sb800_lpc_port80(void);
  55void sb800_pci_port80(void);
  56void sb800_clk_output_48Mhz(void);
  57
  58int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
  59int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
  60
  61void enable_usbdebug(unsigned int port);
  62#else
  63void sb800_enable(device_t dev);
  64void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);
  65#endif
  66
  67#endif /* SB800_H */
  68