1/* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21#if !defined (__PRE_RAM__) 22// HACK 23static inline void cn700_noop(device_t dev) 24{ 25} 26#endif 27 28/* VGA stuff */ 29#define SR_INDEX 0x3c4 30#define SR_DATA 0x3c5 31#define CRTM_INDEX 0x3b4 32#define CRTM_DATA 0x3b5 33#define CRTC_INDEX 0x3d4 34#define CRTC_DATA 0x3d5 35 36/* Memory controller registers */ 37#define RANK0_END 0x40 38#define RANK1_END 0x41 39#define RANK2_END 0x42 40#define RANK3_END 0x43 41#define RANK0_START 0x48 42#define RANK1_START 0x49 43#define RANK2_START 0x4a 44#define RANK3_START 0x4b 45#define DDR_PAGE_CTL 0x69 46#define DRAM_REFRESH_COUNTER 0x6a 47#define DRAM_MISC_CTL 0x6b 48#define CH_A_DQS_OUTPUT_DELAY 0x70 49#define CH_A_MD_OUTPUT_DELAY 0x71 50 51/* RAM init commands */ 52#define RAM_COMMAND_NORMAL 0x0 53#define RAM_COMMAND_NOP 0x1 54#define RAM_COMMAND_PRECHARGE 0x2 55#define RAM_COMMAND_MRS 0x3 56#define RAM_COMMAND_CBR 0x4 57