1/* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21/* 22 * Datasheet: 23 * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller 24 * - URL: http://www.intel.com/design/chipsets/datashts/290633.htm 25 * - PDF: http://www.intel.com/design/chipsets/datashts/29063301.pdf 26 * - Order Number: 290633-001 27 */ 28 29/* 30 * Host-to-PCI Bridge Registers. 31 * The values in parenthesis are the default values as per datasheet. 32 * Any addresses between 0x00 and 0xff not listed below are either 33 * Reserved or Intel Reserved and should not be touched. 34 */ 35 36#define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ 37#define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ 38#define DRAMT 0x58 /* DRAM Timing (0x03). */ 39#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ 40#define PAM0 0x59 41#define PAM1 0x5a 42#define PAM2 0x5b 43#define PAM3 0x5c 44#define PAM4 0x5d 45#define PAM5 0x5e 46#define PAM6 0x5f 47#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ 48#define DRB0 0x60 49#define DRB1 0x61 50#define DRB2 0x62 51#define DRB3 0x63 52#define DRB4 0x64 53#define DRB5 0x65 54#define DRB6 0x66 55#define DRB7 0x67 56#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ 57#define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */ 58#define SMRAM 0x72 /* System Management RAM Control (0x02). */ 59#define ESMRAMC 0x73 /* Extended System Management RAM Control (0x38). */ 60#define RPS 0x74 /* SDRAM Row Page Size (0x0000). */ 61#define SDRAMC 0x76 /* SDRAM Control Register (0x0000). */ 62#define PGPOL 0x78 /* Paging Policy Register (0x00). */ 63#define PMCR 0x7a /* Power Management Control Register (0000_S0S0b). */ 64#define SCRR 0x7b /* Suspend CBR Refresh Rate Register (0x0038). */ 65#define EAP 0x80 /* Error Address Pointer Register (0x00000000). */ 66#define ERRCMD 0x90 /* Error Command Register (0x80). */ 67#define ERRSTS 0x91 /* Error Status (0x0000). */ 68// TODO: AGP stuff. 69#define ACAPID 0xa0 /* AGP Capability Identifier (0x00100002 or 0x00000000) */ 70#define AGPSTAT 0xa4 /* AGP Status Register (0x1f000203, read only) */ 71#define AGPCMD 0xa8 /* AGP Command Register (0x00000000) */ 72#define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */ 73#define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */ 74#define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */ 75 76#define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ 77#define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ 78#define BSPAD0 0xd0 /* These are free for our use. */ 79#define BSPAD1 0xd1 80#define BSPAD2 0xd2 81#define BSPAD3 0xd3 82#define BSPAD4 0xd4 83#define BSPAD5 0xd5 84#define BSPAD6 0xd6 85#define BSPAD7 0xd7 86#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ 87#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ 88#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ 89 90