LXR coreboot/src/northbridge/intel/i3100/raminit.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
   5 * Copyright (C) 2008 Arastra, Inc.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 *
  20 */
  21
  22#include <cpu/x86/mtrr.h>
  23#include <cpu/x86/cache.h>
  24#include <stdlib.h>
  25#include "raminit.h"
  26#include "i3100.h"
  27
  28/* DDR2 memory controller register space */
  29#define MCBAR 0x90000000
  30
  31static void sdram_set_registers(const struct mem_controller *ctrl)
  32{
  33        static const u32 register_values[] = {
  34
  35                /* CKDIS 0x8c disable clocks */
  36        PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
  37
  38                /* 0x9c Device present and extended RAM control
  39                 * DEVPRES is very touchy, hard code the initialization
  40                 * of PCI-E ports here.
  41                 */
  42        PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
  43
  44                /* 0xc8 Remap RAM base and limit off */
  45        PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
  46
  47                /* ??? */
  48        PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
  49        PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
  50
  51                /* 0x50 scrub */
  52        PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
  53
  54                /* 0x58 0x5c PAM */
  55        PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
  56        PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
  57
  58                /* 0xf4 */
  59        PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
  60
  61                /* 0x14 */
  62        PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
  63        };
  64        int i;
  65        int max;
  66
  67        max = ARRAY_SIZE(register_values);
  68        for(i = 0; i < max; i += 3) {
  69                device_t dev;
  70                u32 where;
  71                u32 reg;
  72                dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
  73                where = register_values[i] & 0xff;
  74                reg = pci_read_config32(dev, where);
  75                reg &= register_values[i+1];
  76                reg |= register_values[i+2];
  77                pci_write_config32(dev, where, reg);
  78        }
  79        print_spew("done.\n");
  80}
  81
  82struct dimm_size {
  83        u32 side1;
  84        u32 side2;
  85};
  86
  87static struct dimm_size spd_get_dimm_size(u16 device)
  88{
  89        /* Calculate the log base 2 size of a DIMM in bits */
  90        struct dimm_size sz;
  91        int value, low;
  92        sz.side1 = 0;
  93        sz.side2 = 0;
  94
  95        /* Note it might be easier to use byte 31 here, it has the DIMM size as
  96         * a multiple of 4MB.  The way we do it now we can size both
  97         * sides of an assymetric dimm.
  98         */
  99        value = spd_read_byte(device, 3);       /* rows */
 100        if (value < 0) goto hw_err;
 101        if ((value & 0xf) == 0) goto val_err;
 102        sz.side1 += value & 0xf;
 103
 104        value = spd_read_byte(device, 4);       /* columns */
 105        if (value < 0) goto hw_err;
 106        if ((value & 0xf) == 0) goto val_err;
 107        sz.side1 += value & 0xf;
 108
 109        value = spd_read_byte(device, 17);      /* banks */
 110        if (value < 0) goto hw_err;
 111        if ((value & 0xff) == 0) goto val_err;
 112        sz.side1 += log2(value & 0xff);
 113
 114        /* Get the module data width and convert it to a power of two */
 115        value = spd_read_byte(device, 7);       /* (high byte) */
 116        if (value < 0) goto hw_err;
 117        value &= 0xff;
 118        value <<= 8;
 119
 120        low = spd_read_byte(device, 6); /* (low byte) */
 121        if (low < 0) goto hw_err;
 122        value = value | (low & 0xff);
 123        if ((value != 72) && (value != 64)) goto val_err;
 124        sz.side1 += log2(value);
 125
 126        /* side 2 */
 127        value = spd_read_byte(device, 5);       /* number of physical banks */
 128
 129        if (value < 0) goto hw_err;
 130        value &= 7;
 131        value++;
 132        if (value == 1) goto out;
 133        if (value != 2) goto val_err;
 134
 135        /* Start with the symmetrical case */
 136        sz.side2 = sz.side1;
 137
 138        value = spd_read_byte(device, 3);       /* rows */
 139        if (value < 0) goto hw_err;
 140        if ((value & 0xf0) == 0) goto out;      /* If symmetrical we are done */
 141        sz.side2 -= (value & 0x0f);             /* Subtract out rows on side 1 */
 142        sz.side2 += ((value >> 4) & 0x0f);      /* Add in rows on side 2 */
 143
 144        value = spd_read_byte(device, 4);       /* columns */
 145        if (value < 0) goto hw_err;
 146        if ((value & 0xff) == 0) goto val_err;
 147        sz.side2 -= (value & 0x0f);             /* Subtract out columns on side 1 */
 148        sz.side2 += ((value >> 4) & 0x0f);      /* Add in columns on side 2 */
 149        goto out;
 150
 151 val_err:
 152        die("Bad SPD value\n");
 153        /* If an hw_error occurs report that I have no memory */
 154 hw_err:
 155        sz.side1 = 0;
 156        sz.side2 = 0;
 157 out:
 158        return sz;
 159
 160}
 161
 162static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
 163{
 164        int i;
 165        int cum;
 166
 167        for(i = cum = 0; i < DIMM_SOCKETS; i++) {
 168                struct dimm_size sz;
 169                if (dimm_mask & (1 << i)) {
 170                        sz = spd_get_dimm_size(ctrl->channel0[i]);
 171                        if (sz.side1 < 29) {
 172                                return -1; /* Report SPD error */
 173                        }
 174                        /* convert bits to multiples of 64MB */
 175                        sz.side1 -= 29;
 176                        cum += (1 << sz.side1);
 177                        /* DRB = 0x60 */
 178                        pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 179                        if( sz.side2 > 28) {
 180                                sz.side2 -= 29;
 181                                cum += (1 << sz.side2);
 182                        }
 183                        pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 184                }
 185                else {
 186                        pci_write_config8(ctrl->f0, DRB + (i*2), cum);
 187                        pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
 188                }
 189        }
 190        cum >>= 1;
 191        /* set TOM top of memory 0xcc */
 192        pci_write_config16(ctrl->f0, TOM, cum);
 193        /* set TOLM top of low memory */
 194        if(cum > 0x18) {
 195                cum = 0x18;
 196        }
 197        cum <<= 11;
 198        /* 0xc4 TOLM */
 199        pci_write_config16(ctrl->f0, TOLM, cum);
 200        return 0;
 201}
 202
 203
 204static u32 spd_detect_dimms(const struct mem_controller *ctrl)
 205{
 206        u32 dimm_mask;
 207        int i;
 208        dimm_mask = 0;
 209        for(i = 0; i < DIMM_SOCKETS; i++) {
 210                int byte;
 211                u16 device;
 212                device = ctrl->channel0[i];
 213                if (device) {
 214                        byte = spd_read_byte(device, 2);  /* Type */
 215                        if (byte == 8) {
 216                                dimm_mask |= (1 << i);
 217                        }
 218                }
 219                device = ctrl->channel1[i];
 220                if (device) {
 221                        byte = spd_read_byte(device, 2);
 222                        if (byte == 8) {
 223                                dimm_mask |= (1 << (i + DIMM_SOCKETS));
 224                        }
 225                }
 226        }
 227        return dimm_mask;
 228}
 229
 230
 231static int spd_set_row_attributes(const struct mem_controller *ctrl,
 232                long dimm_mask)
 233{
 234        int value;
 235        int reg;
 236        int dra;
 237        int cnt;
 238
 239        dra = 0;
 240        for(cnt=0; cnt < 4; cnt++) {
 241                if (!(dimm_mask & (1 << cnt))) {
 242                        continue;
 243                }
 244                reg =0;
 245                value = spd_read_byte(ctrl->channel0[cnt], 3);  /* rows */
 246                if (value < 0) goto hw_err;
 247                if ((value & 0xf) == 0) goto val_err;
 248                reg += value & 0xf;
 249
 250                value = spd_read_byte(ctrl->channel0[cnt], 4);  /* columns */
 251                if (value < 0) goto hw_err;
 252                if ((value & 0xf) == 0) goto val_err;
 253                reg += value & 0xf;
 254
 255                value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
 256                if (value < 0) goto hw_err;
 257                if ((value & 0xff) == 0) goto val_err;
 258                reg += log2(value & 0xff);
 259
 260                /* Get the device width and convert it to a power of two */
 261                value = spd_read_byte(ctrl->channel0[cnt], 13);
 262                if (value < 0) goto hw_err;
 263                value = log2(value & 0xff);
 264                reg += value;
 265                if(reg < 27) goto hw_err;
 266                reg -= 27;
 267                reg += (value << 2);
 268
 269                dra += reg << (cnt*8);
 270                value = spd_read_byte(ctrl->channel0[cnt], 5);
 271                if (value & 2)
 272                        dra += reg << ((cnt*8)+4);
 273        }
 274
 275        /* 0x70 DRA */
 276        pci_write_config32(ctrl->f0, DRA, dra);
 277        goto out;
 278
 279 val_err:
 280        die("Bad SPD value\n");
 281        /* If an hw_error occurs report that I have no memory */
 282 hw_err:
 283        dra = 0;
 284 out:
 285        return dra;
 286
 287}
 288
 289
 290static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 291                long dimm_mask, u32 drc)
 292{
 293        int value;
 294        int reg;
 295        u32 drt;
 296        int cnt;
 297        int first_dimm;
 298        int cas_latency=0;
 299        int latency;
 300        u32 index = 0;
 301        u32 index2 = 0;
 302        static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 };
 303        static const u8 latency_indicies[] = { 26, 23, 9 };
 304
 305        /* 0x78 DRT */
 306        drt = pci_read_config32(ctrl->f0, DRT);
 307        drt &= 3;  /* save bits 1:0 */
 308
 309        for(first_dimm = 0; first_dimm < 4; first_dimm++) {
 310                if (dimm_mask & (1 << first_dimm))
 311                        break;
 312        }
 313
 314        drt |= (1<<6); /* back to back write turn around */
 315
 316        drt |= (3<<18);  /* Trasmax */
 317
 318        for(cnt=0; cnt < 4; cnt++) {
 319                if (!(dimm_mask & (1 << cnt))) {
 320                        continue;
 321                }
 322                reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
 323                /* Compute the lowest cas latency supported */
 324                latency = log2(reg) -2;
 325
 326                /* Loop through and find a fast clock with a low latency */
 327                for(index = 0; index < 3; index++, latency++) {
 328                        if ((latency < 2) || (latency > 4) ||
 329                                (!(reg & (1 << latency)))) {
 330                                continue;
 331                        }
 332                        value = spd_read_byte(ctrl->channel0[cnt],
 333                                        latency_indicies[index]);
 334
 335                        if(value <= cycle_time[drc&3]) {
 336                                if( latency > cas_latency) {
 337                                        cas_latency = latency;
 338                                }
 339                                break;
 340                        }
 341                }
 342        }
 343        index = (cas_latency-2);
 344        if((index)==0) cas_latency = 20;
 345        else if((index)==1) cas_latency = 25;
 346        else cas_latency = 30;
 347
 348        for(cnt=0;cnt<4;cnt++) {
 349                if (!(dimm_mask & (1 << cnt))) {
 350                        continue;
 351                }
 352                reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
 353                if(((index>>8)&0x0ff)<reg) {
 354                        index &= ~(0x0ff << 8);
 355                        index |= (reg << 8);
 356                }
 357                reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
 358                if(((index>>16)&0x0ff)<reg) {
 359                        index &= ~(0x0ff << 16);
 360                        index |= (reg<<16);
 361                }
 362                reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
 363                if(((index2>>0)&0x0ff)<reg) {
 364                        index2 &= ~(0x0ff << 0);
 365                        index2 |= (reg<<0);
 366                }
 367                reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
 368                if(((index2>>8)&0x0ff)<reg) {
 369                        index2 &= ~(0x0ff << 8);
 370                        index2 |= (reg<<8);
 371                }
 372                reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
 373                if(((index2>>16)&0x0ff)<reg) {
 374                        index2 &= ~(0x0ff << 16);
 375                        index2 |= (reg<<16);
 376                }
 377        }
 378
 379        /* get dimm speed */
 380        value = cycle_time[drc&3];
 381        if(value <= 0x50) {  /* 200 MHz */
 382                if((index&7) > 2) {
 383                        drt |= (2<<2);  /* CAS latency 4 */
 384                        cas_latency = 40;
 385                } else {
 386                        drt |= (1<<2);  /* CAS latency 3 */
 387                        cas_latency = 30;
 388                }
 389                if((index&0x0ff00)<=0x03c00) {
 390                        drt |= (1<<8);  /* Trp RAS Precharg */
 391                } else {
 392                        drt |= (2<<8);  /* Trp RAS Precharg */
 393                }
 394
 395                /* Trcd RAS to CAS delay */
 396                if((index2&0x0ff)<=0x03c) {
 397                        drt |= (0<<10);
 398                } else {
 399                        drt |= (1<<10);
 400                }
 401
 402                /* Tdal Write auto precharge recovery delay */
 403                drt |= (1<<12);
 404
 405                /* Trc TRS min */
 406                if((index2&0x0ff00)<=0x03700)
 407                        drt |= (0<<14);
 408                else if((index2&0xff00)<=0x03c00)
 409                        drt |= (1<<14);
 410                else
 411                        drt |= (2<<14); /* spd 41 */
 412
 413                drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 414
 415                /* Trrd Row Delay */
 416                if((index&0x0ff0000)<=0x0140000) {
 417                        drt |= (0<<20);
 418                } else if((index&0x0ff0000)<=0x0280000) {
 419                        drt |= (1<<20);
 420                } else if((index&0x0ff0000)<=0x03c0000) {
 421                        drt |= (2<<20);
 422                } else {
 423                        drt |= (3<<20);
 424                }
 425
 426                /* Trfc Auto refresh cycle time */
 427                if((index2&0x0ff0000)<=0x04b0000) {
 428                        drt |= (0<<22);
 429                } else if((index2&0x0ff0000)<=0x0690000) {
 430                        drt |= (1<<22);
 431                } else {
 432                        drt |= (2<<22);
 433                }
 434                /* Docs say use 55 for all 200Mhz */
 435                drt |= (0x055<<24);
 436        }
 437        else if(value <= 0x60) { /* 167 Mhz */
 438                /* according to new documentation CAS latency is 00
 439                 * for bits 3:2 for all 167 Mhz
 440                drt |= ((index&3)<<2); */  /* set CAS latency */
 441                if((index&0x0ff00)<=0x03000) {
 442                        drt |= (1<<8);  /* Trp RAS Precharg */
 443                } else {
 444                        drt |= (2<<8);  /* Trp RAS Precharg */
 445                }
 446
 447                /* Trcd RAS to CAS delay */
 448                if((index2&0x0ff)<=0x030) {
 449                        drt |= (0<<10);
 450                } else {
 451                        drt |= (1<<10);
 452                }
 453
 454                /* Tdal Write auto precharge recovery delay */
 455                drt |= (2<<12);
 456
 457                /* Trc TRS min */
 458                drt |= (2<<14); /* spd 41, but only one choice */
 459
 460                drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 461
 462                /* Trrd Row Delay */
 463                if((index&0x0ff0000)<=0x0180000) {
 464                        drt |= (0<<20);
 465                } else if((index&0x0ff0000)<=0x0300000) {
 466                        drt |= (1<<20);
 467                } else {
 468                        drt |= (2<<20);
 469                }
 470
 471                /* Trfc Auto refresh cycle time */
 472                if((index2&0x0ff0000)<=0x0480000) {
 473                        drt |= (0<<22);
 474                } else if((index2&0x0ff0000)<=0x0780000) {
 475                        drt |= (2<<22);
 476                } else {
 477                        drt |= (2<<22);
 478                }
 479                /* Docs state to use 99 for all 167 Mhz */
 480                drt |= (0x099<<24);
 481        }
 482        else if(value <= 0x75) { /* 133 Mhz */
 483                drt |= ((index&3)<<2);  /* set CAS latency */
 484                if((index&0x0ff00)<=0x03c00) {
 485                        drt |= (1<<8);  /* Trp RAS Precharg */
 486                } else {
 487                        drt |= (2<<8);  /* Trp RAS Precharg */
 488                }
 489
 490                /* Trcd RAS to CAS delay */
 491                if((index2&0x0ff)<=0x03c) {
 492                        drt |= (0<<10);
 493                } else {
 494                        drt |= (1<<10);
 495                }
 496
 497                /* Tdal Write auto precharge recovery delay */
 498                drt |= (1<<12);
 499
 500                /* Trc TRS min */
 501                drt |= (2<<14); /* spd 41, but only one choice */
 502
 503                drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 504
 505                /* Trrd Row Delay */
 506                if((index&0x0ff0000)<=0x01e0000) {
 507                        drt |= (0<<20);
 508                } else if((index&0x0ff0000)<=0x03c0000) {
 509                        drt |= (1<<20);
 510                } else {
 511                        drt |= (2<<20);
 512                }
 513
 514                /* Trfc Auto refresh cycle time */
 515                if((index2&0x0ff0000)<=0x04b0000) {
 516                        drt |= (0<<22);
 517                } else if((index2&0x0ff0000)<=0x0780000) {
 518                        drt |= (2<<22);
 519                } else {
 520                        drt |= (2<<22);
 521                }
 522
 523                /* Based on CAS latency */
 524                if(index&7)
 525                        drt |= (0x099<<24);
 526                else
 527                        drt |= (0x055<<24);
 528
 529        }
 530        else {
 531                die("Invalid SPD 9 bus speed.\n");
 532        }
 533
 534        /* 0x78 DRT */
 535        pci_write_config32(ctrl->f0, DRT, drt);
 536
 537        return(cas_latency);
 538}
 539
 540static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 541                long dimm_mask)
 542{
 543        int value;
 544        int drc;
 545        int cnt;
 546        msr_t msr;
 547        u8 rate = 62;
 548        static const u8 spd_rates[6] = {15,3,7,7,62,62};
 549        static const u8 drc_rates[5] = {0,15,7,62,3};
 550        static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3};
 551
 552        /* 0x7c DRC */
 553        drc = pci_read_config32(ctrl->f0, DRC);
 554        for(cnt=0; cnt < 4; cnt++) {
 555                if (!(dimm_mask & (1 << cnt))) {
 556                        continue;
 557                }
 558                value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
 559                if (value != 2) die("ERROR - Non ECC memory dimm\n");
 560
 561                value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
 562                value &= 0x0f;    /* clip self refresh bit */
 563                if (value > 5) goto hw_err;
 564                if (rate > spd_rates[value])
 565                        rate = spd_rates[value];
 566
 567                value = spd_read_byte(ctrl->channel0[cnt], 9);  /* cycle time */
 568                if (value > 0x75) goto hw_err;
 569        }
 570        drc |= (1 << 20); /* enable ECC */
 571        for (cnt = 1; cnt < 5; cnt++)
 572                if (drc_rates[cnt] == rate)
 573                        break;
 574        if (cnt < 5) {
 575                drc &= ~(7 << 8);  /* clear the rate bits */
 576                drc |= (cnt << 8);
 577        }
 578
 579        drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
 580        drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
 581        drc |= (1 << 7);
 582        drc &= ~(1 << 5); /* enable ODT */
 583        drc |= (1 << 4); /* independent clocks */
 584
 585        /* set front side bus speed */
 586        msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
 587        value = msr.lo & 0x07;
 588        drc &= ~(3 << 2);
 589        drc |= (fsb_conversion[value] << 2);
 590
 591        /* set dram type to ddr2 */
 592        drc &= ~(3 << 0);
 593        drc |= (2 << 0);
 594
 595        goto out;
 596
 597        /* If an hw_error occurs report that I have no memory */
 598 hw_err:
 599        drc = 0;
 600 out:
 601        return drc;
 602}
 603
 604static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 605{
 606        long dimm_mask;
 607
 608        /* Test if we can read the spd and if ram is ddr or ddr2 */
 609        dimm_mask = spd_detect_dimms(ctrl);
 610        if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 611                print_err("No memory for this cpu\n");
 612                return;
 613        }
 614        return;
 615}
 616
 617static void do_delay(void)
 618{
 619        int i;
 620        u8 b;
 621        for(i=0;i<16;i++)
 622                b=inb(0x80);
 623}
 624
 625#define TIMEOUT_LOOPS 300000
 626
 627#define DCALCSR  0x100
 628#define DCALADDR 0x104
 629#define DCALDATA 0x108
 630
 631static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 632{
 633        u8 c1,c2;
 634        u32 dimm,i;
 635        u32 data32;
 636        u32 t4;
 637
 638        /* Set up northbridge values */
 639        /* ODT enable */
 640        pci_write_config32(ctrl->f0, SDRC, 0x30000000);
 641        /* Figure out which slots are Empty, Single, or Double sided */
 642        for(i=0,t4=0,c2=0;i<8;i+=2) {
 643                c1 = pci_read_config8(ctrl->f0, DRB+i);
 644                if(c1 == c2) continue;
 645                c2 = pci_read_config8(ctrl->f0, DRB+1+i);
 646                if(c1 == c2)
 647                        t4 |= (1 << (i*4));
 648                else
 649                        t4 |= (2 << (i*4));
 650        }
 651        for(i=0;i<1;i++) {
 652            if((t4&0x0f) == 1) {
 653                if( ((t4>>8)&0x0f) == 0 ) {
 654                        data32 = 0x00000010; /* EEES */
 655                        break;
 656                }
 657                if ( ((t4>>16)&0x0f) == 0 ) {
 658                        data32 = 0x00003132; /* EESS */
 659                        break;
 660                }
 661                if ( ((t4>>24)&0x0f)  == 0 ) {
 662                        data32 = 0x00335566; /* ESSS */
 663                        break;
 664                }
 665                data32 = 0x77bbddee; /* SSSS */
 666                break;
 667            }
 668            if((t4&0x0f) == 2) {
 669                if( ((t4>>8)&0x0f) == 0 ) {
 670                        data32 = 0x00003132; /* EEED */
 671                        break;
 672                }
 673                if ( ((t4>>8)&0x0f) == 2 ) {
 674                        data32 = 0xb373ecdc; /* EEDD */
 675                        break;
 676                }
 677                if ( ((t4>>16)&0x0f) == 0 ) {
 678                        data32 = 0x00b3a898; /* EESD */
 679                        break;
 680                }
 681                data32 = 0x777becdc; /* ESSD */
 682                break;
 683            }
 684            die("Error - First dimm slot empty\n");
 685        }
 686
 687        print_debug("ODT Value = ");
 688        print_debug_hex32(data32);
 689        print_debug("\n");
 690
 691        pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 692
 693        for(dimm=0;dimm<8;dimm+=2) {
 694
 695                write32(MCBAR+DCALADDR, 0x0b840001);
 696                write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
 697
 698                for(i=0;i<1001;i++) {
 699                        data32 = read32(MCBAR+DCALCSR);
 700                        if(!(data32 & (1<<31)))
 701                                break;
 702                }
 703        }
 704}
 705static void set_receive_enable(const struct mem_controller *ctrl)
 706{
 707        u32 i;
 708        u32 cnt;
 709        u32 recena=0;
 710        u32 recenb=0;
 711
 712        {
 713        u32 dimm;
 714        u32 edge;
 715        int32_t data32;
 716        u32 dcal_data32_0;
 717        u32 dcal_data32_1;
 718        u32 dcal_data32_2;
 719        u32 dcal_data32_3;
 720        u32 work32l;
 721        u32 work32h;
 722        u32 data32r;
 723        int32_t recen;
 724        for(dimm=0;dimm<8;dimm+=1) {
 725
 726                if(!(dimm&1)) {
 727                        write32(MCBAR+DCALDATA+(17*4), 0x04020000);
 728                        write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
 729
 730                        for(i=0;i<1001;i++) {
 731                                data32 = read32(MCBAR+DCALCSR);
 732                                if(!(data32 & (1<<31)))
 733                                        break;
 734                        }
 735                        if(i>=1000)
 736                                continue;
 737
 738                        dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
 739                        dcal_data32_1 = read32(MCBAR+DCALDATA + 4);
 740                        dcal_data32_2 = read32(MCBAR+DCALDATA + 8);
 741                        dcal_data32_3 = read32(MCBAR+DCALDATA + 12);
 742                }
 743                else {
 744                        dcal_data32_0 = read32(MCBAR+DCALDATA + 16);
 745                        dcal_data32_1 = read32(MCBAR+DCALDATA + 20);
 746                        dcal_data32_2 = read32(MCBAR+DCALDATA + 24);
 747                        dcal_data32_3 = read32(MCBAR+DCALDATA + 28);
 748                }
 749
 750                /* check if bank is installed */
 751                if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 752                        continue;
 753                /* Calculate the timing value */
 754                {
 755                u32 bit;
 756                for(i=0,edge=0,bit=63,cnt=31,data32r=0,
 757                        work32l=dcal_data32_1,work32h=dcal_data32_3;
 758                                (i<4) && bit; i++) {
 759                        for(;;bit--,cnt--) {
 760                                if(work32l & (1<<cnt))
 761                                        break;
 762                                if(!cnt) {
 763                                        work32l = dcal_data32_0;
 764                                        work32h = dcal_data32_2;
 765                                        cnt = 32;
 766                                }
 767                                if(!bit) break;
 768                        }
 769                        for(;;bit--,cnt--) {
 770                                if(!(work32l & (1<<cnt)))
 771                                        break;
 772                                if(!cnt) {
 773                                        work32l = dcal_data32_0;
 774                                        work32h = dcal_data32_2;
 775                                        cnt = 32;
 776                                }
 777                                if(!bit) break;
 778                        }
 779                        if(!bit) {
 780                                break;
 781                        }
 782                        data32 = ((bit%8) << 1);
 783                        if(work32h & (1<<cnt))
 784                                data32 += 1;
 785                        if(data32 < 4) {
 786                                if(!edge) {
 787                                        edge = 1;
 788                                }
 789                                else {
 790                                        if(edge != 1) {
 791                                                data32 = 0x0f;
 792                                        }
 793                                }
 794                        }
 795                        if(data32 > 12) {
 796                                if(!edge) {
 797                                        edge = 2;
 798                                }
 799                                else {
 800                                        if(edge != 2) {
 801                                                data32 = 0x00;
 802                                        }
 803                                }
 804                        }
 805                        data32r += data32;
 806                }
 807                }
 808                work32l = dcal_data32_0;
 809                work32h = dcal_data32_2;
 810                recen = data32r;
 811                recen += 3;
 812                recen = recen>>2;
 813                for(cnt=5;cnt<24;) {
 814                        for(;;cnt++)
 815                                if(!(work32l & (1<<cnt)))
 816                                        break;
 817                        for(;;cnt++) {
 818                                if(work32l & (1<<cnt))
 819                                        break;
 820                        }
 821                        data32 = (((cnt-1)%8)<<1);
 822                        if(work32h & (1<<(cnt-1))) {
 823                                data32++;
 824                        }
 825                        /* test for frame edge cross overs */
 826                        if((edge == 1) && (data32 > 12) &&
 827                            (((recen+16)-data32) < 3)) {
 828                                data32 = 0;
 829                                cnt += 2;
 830                        }
 831                        if((edge == 2) && (data32 < 4) &&
 832                            ((recen - data32) > 12))  {
 833                                data32 = 0x0f;
 834                                cnt -= 2;
 835                        }
 836                        if(((recen+3) >= data32) && ((recen-3) <= data32))
 837                                break;
 838                }
 839                cnt--;
 840                cnt /= 8;
 841                cnt--;
 842                if(recen&1)
 843                        recen+=2;
 844                recen >>= 1;
 845                recen += (cnt*8);
 846                recen+=2;      /* this is not in the spec, but matches
 847                                 the factory output, and has less failure */
 848                recen <<= (dimm/2) * 8;
 849                if(!(dimm&1)) {
 850                        recena |= recen;
 851                }
 852                else {
 853                        recenb |= recen;
 854                }
 855        }
 856        }
 857        /* Check for Eratta problem */
 858        for(i=cnt=0;i<32;i+=8) {
 859                if (((recena>>i)&0x0f)>7) {
 860                        cnt+= 0x101;
 861                }
 862                else {
 863                        if((recena>>i)&0x0f) {
 864                                cnt++;
 865                        }
 866                }
 867        }
 868        if(cnt&0x0f00) {
 869                cnt = (cnt&0x0f) - (cnt>>16);
 870                if(cnt>1) {
 871                        for(i=0;i<32;i+=8) {
 872                                if(((recena>>i)&0x0f)>7) {
 873                                        recena &= ~(0x0f<<i);
 874                                        recena |= (7<<i);
 875                                }
 876                        }
 877                }
 878                else {
 879                        for(i=0;i<32;i+=8) {
 880                                if(((recena>>i)&0x0f)<8) {
 881                                        recena &= ~(0x0f<<i);
 882                                        recena |= (8<<i);
 883                                }
 884                        }
 885                }
 886        }
 887        for(i=cnt=0;i<32;i+=8) {
 888                if (((recenb>>i)&0x0f)>7) {
 889                        cnt+= 0x101;
 890                }
 891                else {
 892                        if((recenb>>i)&0x0f) {
 893                                cnt++;
 894                        }
 895                }
 896        }
 897        if(cnt & 0x0f00) {
 898                cnt = (cnt&0x0f) - (cnt>>16);
 899                if(cnt>1) {
 900                        for(i=0;i<32;i+=8) {
 901                                if(((recenb>>i)&0x0f)>7) {
 902                                        recenb &= ~(0x0f<<i);
 903                                        recenb |= (7<<i);
 904                                }
 905                        }
 906                }
 907                else {
 908                        for(i=0;i<32;i+=8) {
 909                                if(((recenb>>8)&0x0f)<8) {
 910                                        recenb &= ~(0x0f<<i);
 911                                        recenb |= (8<<i);
 912                                }
 913                        }
 914                }
 915        }
 916
 917        print_debug("Receive enable A = ");
 918        print_debug_hex32(recena);
 919        print_debug(",  Receive enable B = ");
 920        print_debug_hex32(recenb);
 921        print_debug("\n");
 922
 923        /* clear out the calibration area */
 924        write32(MCBAR+DCALDATA+(16*4), 0x00000000);
 925        write32(MCBAR+DCALDATA+(17*4), 0x00000000);
 926        write32(MCBAR+DCALDATA+(18*4), 0x00000000);
 927        write32(MCBAR+DCALDATA+(19*4), 0x00000000);
 928
 929        /* No command */
 930        write32(MCBAR+DCALCSR, 0x0000000f);
 931
 932        write32(MCBAR+0x150, recena);
 933        write32(MCBAR+0x154, recenb);
 934}
 935
 936
 937static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 938{
 939        int i;
 940        int cs;
 941        int cnt;
 942        int cas_latency;
 943        long mask;
 944        u32 drc;
 945        u32 data32;
 946        u32 mode_reg;
 947        const u32 *iptr;
 948        u16 data16;
 949        static const struct {
 950                u32 clkgr[4];
 951        } gearing [] = {
 952                /* FSB 100 */
 953        {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}},
 954                /* FSB 133 */
 955        {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
 956                /* FSB 167 */
 957        {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
 958                /* FSB 200 DIMM 400 */
 959        {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
 960        };
 961
 962        static const u32 dqs_data[] = {
 963                0xffffffff, 0xffffffff, 0x000000ff,
 964                0xffffffff, 0xffffffff, 0x000000ff,
 965                0xffffffff, 0xffffffff, 0x000000ff,
 966                0xffffffff, 0xffffffff, 0x000000ff,
 967                0xffffffff, 0xffffffff, 0x000000ff,
 968                0xffffffff, 0xffffffff, 0x000000ff,
 969                0xffffffff, 0xffffffff, 0x000000ff,
 970                0xffffffff, 0xffffffff, 0x000000ff};
 971
 972        mask = spd_detect_dimms(ctrl);
 973        print_debug("Starting SDRAM Enable\n");
 974
 975        /* 0x80 */
 976        pci_write_config32(ctrl->f0, DRM,
 977                0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
 978        /* set dram type and Front Side Bus freq. */
 979        drc = spd_set_dram_controller_mode(ctrl, mask);
 980        if( drc == 0) {
 981                die("Error calculating DRC\n");
 982        }
 983        data32 = drc & ~(3 << 20);  /* clear ECC mode */
 984        data32 = data32 & ~(7 << 8);  /* clear refresh rates */
 985        data32 = data32 | (1 << 5);  /* temp turn off ODT */
 986        /* Set gearing, then dram controller mode */
 987        /* drc bits 3:2 = FSB speed */
 988        for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
 989                pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
 990        }
 991        /* 0x7c DRC */
 992        pci_write_config32(ctrl->f0, DRC, data32);
 993
 994                /* turn the clocks on */
 995        /* 0x8c CKDIS */
 996        pci_write_config16(ctrl->f0, CKDIS, 0x0000);
 997
 998                /* 0x9a DDRCSR Take subsystem out of idle */
 999        data16 = pci_read_config16(ctrl->f0, DDRCSR);
1000        data16 &= ~(7 << 12);

1001        data16 |= (1 << 12);
1002        pci_write_config16(ctrl->f0, DDRCSR, data16);
1003
1004                /* program row size DRB */
1005        spd_set_ram_size(ctrl, mask);
1006
1007                /* program page size DRA */
1008        spd_set_row_attributes(ctrl, mask);
1009
1010                /* program DRT timing values */
1011        cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1012
1013        for(i=0;i<8;i+=2) { /* loop through each dimm to test */
1014                print_debug("DIMM ");
1015                print_debug_hex8(i);
1016                print_debug("\n");
1017                /* Apply NOP */
1018                do_delay();
1019
1020                write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
1021                write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
1022
1023                data32 = read32(MCBAR+DCALCSR);
1024                while(data32 & 0x80000000)
1025                        data32 = read32(MCBAR+DCALCSR);
1026        }
1027
1028        /* Apply NOP */
1029        do_delay();
1030
1031        for(cs=0;cs<8;cs+=2) {
1032                write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
1033                data32 = read32(MCBAR+DCALCSR);
1034                while(data32 & 0x80000000)
1035                        data32 = read32(MCBAR+DCALCSR);
1036        }
1037
1038        /* Precharg all banks */
1039        do_delay();
1040        for(cs=0;cs<8;cs+=2) {
1041                write32(MCBAR+DCALADDR, 0x04000000);
1042                write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1043                data32 = read32(MCBAR+DCALCSR);
1044                while(data32 & 0x80000000)
1045                        data32 = read32(MCBAR+DCALCSR);
1046        }
1047
1048        /* EMRS dll's enabled */
1049        do_delay();
1050        for(cs=0;cs<8;cs+=2) {
1051                /* fixme hard code AL additive latency */
1052                write32(MCBAR+DCALADDR, 0x0b940001);
1053                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1054                data32 = read32(MCBAR+DCALCSR);
1055                while(data32 & 0x80000000)
1056                        data32 = read32(MCBAR+DCALCSR);
1057        }
1058        /* MRS reset dll's */
1059        do_delay();
1060        if(cas_latency == 30)
1061                mode_reg = 0x053a0000;
1062        else
1063                mode_reg = 0x054a0000;
1064        for(cs=0;cs<8;cs+=2) {
1065                write32(MCBAR+DCALADDR, mode_reg);
1066                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1067                data32 = read32(MCBAR+DCALCSR);
1068                while(data32 & 0x80000000)
1069                        data32 = read32(MCBAR+DCALCSR);
1070        }
1071
1072        /* Precharg all banks */
1073        do_delay();
1074        do_delay();
1075        do_delay();
1076        for(cs=0;cs<8;cs+=2) {
1077                write32(MCBAR+DCALADDR, 0x04000000);
1078                write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1079                data32 = read32(MCBAR+DCALCSR);
1080                while(data32 & 0x80000000)
1081                        data32 = read32(MCBAR+DCALCSR);
1082        }
1083
1084        /* Do 2 refreshes */
1085        do_delay();
1086        for(cs=0;cs<8;cs+=2) {
1087                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1088                data32 = read32(MCBAR+DCALCSR);
1089                while(data32 & 0x80000000)
1090                        data32 = read32(MCBAR+DCALCSR);
1091        }
1092        do_delay();
1093        for(cs=0;cs<8;cs+=2) {
1094                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1095                data32 = read32(MCBAR+DCALCSR);
1096                while(data32 & 0x80000000)
1097                        data32 = read32(MCBAR+DCALCSR);
1098        }
1099        do_delay();
1100        /* for good luck do 6 more */
1101        for(cs=0;cs<8;cs+=2) {
1102                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1103        }
1104        do_delay();
1105        for(cs=0;cs<8;cs+=2) {
1106                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1107        }
1108        do_delay();
1109        for(cs=0;cs<8;cs+=2) {
1110                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1111        }
1112        do_delay();
1113        for(cs=0;cs<8;cs+=2) {
1114                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1115        }
1116        do_delay();
1117        for(cs=0;cs<8;cs+=2) {
1118                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1119        }
1120        do_delay();
1121        for(cs=0;cs<8;cs+=2) {
1122                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1123        }
1124        do_delay();
1125        /* MRS reset dll's normal */
1126        do_delay();
1127        for(cs=0;cs<8;cs+=2) {
1128                write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
1129                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1130                data32 = read32(MCBAR+DCALCSR);
1131                while(data32 & 0x80000000)
1132                        data32 = read32(MCBAR+DCALCSR);
1133        }
1134
1135        /* Do only if DDR2  EMRS dll's enabled */
1136        do_delay();
1137        for(cs=0;cs<8;cs+=2) {
1138                write32(MCBAR+DCALADDR, (0x0b940001));
1139                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1140                data32 = read32(MCBAR+DCALCSR);
1141                while(data32 & 0x80000000)
1142                        data32 = read32(MCBAR+DCALCSR);
1143        }
1144
1145        do_delay();
1146        /* No command */
1147        write32(MCBAR+DCALCSR, 0x0000000f);
1148
1149        /* enable on dimm termination */
1150        set_on_dimm_termination_enable(ctrl);
1151
1152        /* receive enable calibration */
1153        set_receive_enable(ctrl);
1154
1155        /* DQS */
1156        pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
1157        for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
1158                write32(cnt, dqs_data[i]);
1159        }
1160        pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
1161
1162        /* Enable refresh */
1163        /* 0x7c DRC */
1164        data32 = drc & ~(3 << 20);  /* clear ECC mode */
1165        pci_write_config32(ctrl->f0, DRC, data32);
1166        write32(MCBAR+DCALCSR, 0x0008000f);
1167
1168        /* clear memory and init ECC */
1169        print_debug("Clearing memory\n");
1170        for(i=0;i<64;i+=4) {
1171                write32(MCBAR+DCALDATA+i, 0x00000000);
1172        }
1173
1174        for(cs=0;cs<8;cs+=2) {
1175                write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
1176                data32 = read32(MCBAR+DCALCSR);
1177                while(data32 & 0x80000000)
1178                        data32 = read32(MCBAR+DCALCSR);
1179        }
1180
1181        /* Bring memory subsystem on line */
1182        data32 = pci_read_config32(ctrl->f0, 0x98);
1183        data32 |= (1 << 31);
1184        pci_write_config32(ctrl->f0, 0x98, data32);
1185        /* wait for completion */
1186        print_debug("Waiting for mem complete\n");
1187        while(1) {
1188                data32 = pci_read_config32(ctrl->f0, 0x98);
1189                if( (data32 & (1<<31)) == 0)
1190                        break;
1191        }
1192        print_debug("Done\n");
1193
1194        /* Set initialization complete */
1195        /* 0x7c DRC */
1196        drc |= (1 << 29);
1197        data32 = drc & ~(3 << 20);  /* clear ECC mode */
1198        pci_write_config32(ctrl->f0, DRC, data32);
1199
1200        /* Set the ecc mode */
1201        pci_write_config32(ctrl->f0, DRC, drc);
1202
1203        /* Enable memory scrubbing */
1204        /* 0x52 MCHSCRB */
1205        data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1206        data16 &= ~0x0f;
1207        data16 |= ((2 << 2) | (2 << 0));
1208        pci_write_config16(ctrl->f0, MCHSCRB, data16);
1209
1210        /* The memory is now setup, use it */
1211#if CONFIG_CACHE_AS_RAM == 0
1212        cache_lbmem(MTRR_TYPE_WRBACK);
1213#endif
1214}
1215