LXR coreboot/src/northbridge/amd/lx/grphinit.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21#include <arch/io.h>
  22#include <stdint.h>
  23#include <cpu/amd/vr.h>
  24#include <console/console.h>
  25#include <cpu/amd/lxdef.h>
  26#include <cpu/x86/msr.h>
  27#include <stdlib.h>
  28
  29void geodelx_vga_msr_init(void);
  30void graphics_init(void);
  31
  32struct msrinit {
  33        u32 msrnum;
  34        msr_t msr;
  35};
  36
  37static const struct msrinit geodelx_vga_msr[] = {
  38        /* Enable the GLIU Memory routing to the hardware
  39        * PDID1 : Port 4, GLIU0
  40        * PBASE : 0x000A0
  41        * PMASK : 0xFFFE0
  42        */
  43        {.msrnum = MSR_GLIU0_BASE4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},
  44        /* Enable the GLIU IO Routing
  45        * IDID  : Port 4, GLIU0
  46        * IBASE : 0x003c0
  47        * IMASK : 0xffff0
  48        */
  49        {.msrnum = GLIU0_IOD_BM_0,  {.lo = 0x3c0ffff0, .hi = 0x80000000}},
  50        /* Enable the GLIU IO Routing
  51        * IDID  : Port 4, GLIU0
  52        * IBASE : 0x003d0
  53        * IMASK : 0xffff0
  54        */
  55        {.msrnum = GLIU0_IOD_BM_1,  {.lo = 0x3d0ffff0, .hi = 0x80000000}},
  56};
  57
  58void geodelx_vga_msr_init(void)
  59{
  60        int i;
  61        for (i = 0; i < ARRAY_SIZE(geodelx_vga_msr); i++)
  62                wrmsr(geodelx_vga_msr[i].msrnum, geodelx_vga_msr[i].msr);
  63}
  64
  65 /*
  66  * This function mirrors the Graphics_Init routine in GeodeROM.
  67  */
  68void graphics_init(void)
  69{
  70        uint16_t wClassIndex, wData, res;
  71
  72        /* SoftVG initialization */
  73        printk(BIOS_DEBUG, "Graphics init...\n");
  74
  75        geodelx_vga_msr_init();
  76
  77        /* Call SoftVG with the main configuration parameters. */
  78        /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
  79
  80        wClassIndex = (VRC_VG << 8) + VG_CONFIG;
  81
  82        /*
  83         * Graphics Driver Enabled (13)                         0, NO (lets BIOS controls the GP)
  84         * External Monochrome Card Support(12)         0, NO
  85         * Controller Priority Select(11)                       1, Primary
  86         * Display Select(10:8)                                         0x0, CRT
  87         * Graphics Memory Size(7:1)                            CONFIG_VIDEO_MB >> 1,
  88         *                                                                                      defined in devicetree.cb
  89         * PLL Reference Clock Bypass(0)                        0, Default
  90         */
  91
  92        /* Video RAM has to be given in 2MB chunks
  93         *   the value is read @ 7:1 (value in 7:0 looks like /2)
  94         *   so we can add the real value in megabytes
  95         */
  96
  97        wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |
  98                        VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
  99        vrWrite(wClassIndex, wData);
 100
 101        res = vrRead(wClassIndex);
 102        printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
 103}
 104