coreboot/src/mainboard/intel/eagleheights/fadt.c
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   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007-2008 coresystems GmbH
   5 * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; version 2 of
  10 * the License.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  20 * MA 02110-1301 USA
  21 */
  22
  23#include <string.h>
  24#include <device/pci.h>
  25#include <arch/acpi.h>
  26
  27#define ACPI_PM1_STS        (pmbase + 0x00)
  28#define ACPI_PM1_EN         (pmbase + 0x02)
  29#define ACPI_PM1_CNT        (pmbase + 0x04)
  30#define ACPI_PM1_TMR        (pmbase + 0x08)
  31#define ACPI_PROC_CNT       (pmbase + 0x10)
  32#define ACPI_LV2            (pmbase + 0x14)
  33#define ACPI_GPE0_STS       (pmbase + 0x28)
  34#define ACPI_GPE0_EN        (pmbase + 0x2C)
  35#define ACPI_SMI_EN         (pmbase + 0x30)
  36#define ACPI_SMI_STS        (pmbase + 0x34)
  37#define ACPI_ALT_GP_SMI_EN  (pmbase + 0x38)
  38#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)
  39#define ACPI_MON_SMI        (pmbase + 0x40)
  40#define ACPI_DEVACT_STS     (pmbase + 0x44)
  41#define ACPI_DEVTRAP_EN     (pmbase + 0x48)
  42#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C)
  43#define ACPI_BUS_CYC_TRACK  (pmbase + 0x4E)
  44
  45#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS
  46#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT
  47#define ACPI_PM_TMR_BLK   ACPI_PM1_TMR
  48#define ACPI_P_BLK        ACPI_PROC_CNT
  49#define ACPI_GPE0_BLK     ACPI_GPE0_STS
  50
  51void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
  52{
  53        acpi_header_t *header = &(fadt->header);
  54        u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
  55
  56        memset((void *) fadt, 0, sizeof(acpi_fadt_t));
  57        memcpy(header->signature, "FACP", 4);
  58        header->length = 244;
  59        header->revision = 3;
  60        memcpy(header->oem_id, "CORE  ", 6);
  61        memcpy(header->oem_table_id, "COREBOOT", 8);
  62        memcpy(header->asl_compiler_id, "CORE", 4);
  63        header->asl_compiler_revision = 0;
  64
  65        fadt->firmware_ctrl = (unsigned long) facs;
  66        fadt->dsdt = (unsigned long) dsdt;
  67        fadt->preferred_pm_profile = 7; /* Performance Server */
  68        fadt->sci_int = 0x9;
  69#if CONFIG_HAVE_SMI_HANDLER == 1
  70        fadt->smi_cmd = 0xb2;
  71#else
  72        fadt->smi_cmd = 0x00;
  73#endif
  74        fadt->acpi_enable = 0xe1;
  75        fadt->acpi_disable = 0x1e;
  76        fadt->s4bios_req = 0x0;
  77        fadt->pstate_cnt = 0xe2;
  78
  79        fadt->pm1a_evt_blk = pmbase;
  80        fadt->pm1b_evt_blk = 0x0;
  81        fadt->pm1a_cnt_blk = pmbase + 0x4;
  82        fadt->pm1b_cnt_blk = 0x0;
  83        fadt->pm2_cnt_blk = 0x0;
  84        fadt->pm_tmr_blk = pmbase + 0x8;
  85        fadt->gpe0_blk = pmbase + 0x28;
  86        fadt->gpe1_blk = 0x0;
  87
  88        fadt->pm1_evt_len = 0x4;
  89        fadt->pm1_cnt_len = 0x2;
  90        fadt->pm2_cnt_len = 0x0;
  91        fadt->pm_tmr_len = 0x4;
  92        fadt->gpe0_blk_len = 0x8;
  93        fadt->gpe1_blk_len = 0x0;
  94        fadt->gpe1_base = 0x0;
  95        fadt->cst_cnt = 0xe3;
  96        fadt->p_lvl2_lat = 0x65;
  97        fadt->p_lvl3_lat = 0x3e9;
  98        fadt->flush_size = 0x400;
  99        fadt->flush_stride = 0x10;
 100        fadt->duty_offset = 0x1;
 101        fadt->duty_width = 0x3;
 102        fadt->day_alrm = 0xd;
 103        fadt->mon_alrm = 0x00;
 104        fadt->century = 0x00;
 105        fadt->iapc_boot_arch = 0x03;
 106        fadt->flags = 0xa5;
 107
 108        fadt->reset_reg.space_id = 1;
 109        fadt->reset_reg.bit_width = 8;
 110        fadt->reset_reg.bit_offset = 0;
 111        fadt->reset_reg.resv = 0;
 112        fadt->reset_reg.addrl = 0xcf9;
 113        fadt->reset_reg.addrh = 0;
 114        fadt->reset_value = 6;
 115        fadt->res3 = 0;
 116        fadt->res4 = 0;
 117        fadt->res5 = 0;
 118        fadt->x_firmware_ctl_l = (u32)facs;
 119        fadt->x_firmware_ctl_h = 0;
 120        fadt->x_dsdt_l = (u32)dsdt;
 121        fadt->x_dsdt_h = 0;
 122
 123        fadt->x_pm1a_evt_blk.space_id = 1;
 124        fadt->x_pm1a_evt_blk.bit_width = 32;
 125        fadt->x_pm1a_evt_blk.bit_offset = 0;
 126        fadt->x_pm1a_evt_blk.resv = 0;
 127        fadt->x_pm1a_evt_blk.addrl = pmbase;
 128        fadt->x_pm1a_evt_blk.addrh = 0x0;
 129
 130        fadt->x_pm1b_evt_blk.space_id = 1;
 131        fadt->x_pm1b_evt_blk.bit_width = 32;
 132        fadt->x_pm1b_evt_blk.bit_offset = 0;
 133        fadt->x_pm1b_evt_blk.resv = 0;
 134        fadt->x_pm1b_evt_blk.addrl = 0x0;
 135        fadt->x_pm1b_evt_blk.addrh = 0x0;
 136
 137        fadt->x_pm1a_cnt_blk.space_id = 1;
 138        fadt->x_pm1a_cnt_blk.bit_width = 16;
 139        fadt->x_pm1a_cnt_blk.bit_offset = 0;
 140        fadt->x_pm1a_cnt_blk.resv = 0;
 141        fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
 142        fadt->x_pm1a_cnt_blk.addrh = 0x0;
 143
 144        fadt->x_pm1b_cnt_blk.space_id = 1;
 145        fadt->x_pm1b_cnt_blk.bit_width = 0;
 146        fadt->x_pm1b_cnt_blk.bit_offset = 0;
 147        fadt->x_pm1b_cnt_blk.resv = 0;
 148        fadt->x_pm1b_cnt_blk.addrl = 0x0;
 149        fadt->x_pm1b_cnt_blk.addrh = 0x0;
 150
 151        fadt->x_pm2_cnt_blk.space_id = 1;
 152        fadt->x_pm2_cnt_blk.bit_width = 0;
 153        fadt->x_pm2_cnt_blk.bit_offset = 0;
 154        fadt->x_pm2_cnt_blk.resv = 0;
 155        fadt->x_pm2_cnt_blk.addrl = 0x0;
 156        fadt->x_pm2_cnt_blk.addrh = 0x0;
 157
 158        fadt->x_pm_tmr_blk.space_id = 1;
 159        fadt->x_pm_tmr_blk.bit_width = 32;
 160        fadt->x_pm_tmr_blk.bit_offset = 0;
 161        fadt->x_pm_tmr_blk.resv = 0;
 162        fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
 163        fadt->x_pm_tmr_blk.addrh = 0x0;
 164
 165        fadt->x_gpe0_blk.space_id = 1;
 166        fadt->x_gpe0_blk.bit_width = 64;
 167        fadt->x_gpe0_blk.bit_offset = 0;
 168        fadt->x_gpe0_blk.resv = 0;
 169        fadt->x_gpe0_blk.addrl = pmbase + 0x28;
 170        fadt->x_gpe0_blk.addrh = 0x0;
 171
 172        fadt->x_gpe1_blk.space_id = 1;
 173        fadt->x_gpe1_blk.bit_width = 32;
 174        fadt->x_gpe1_blk.bit_offset = 0;
 175        fadt->x_gpe1_blk.resv = 0;
 176        fadt->x_gpe1_blk.addrl = 0x0;
 177        fadt->x_gpe1_blk.addrh = 0x0;
 178
 179        header->checksum =
 180            acpi_checksum((void *) fadt, header->length);
 181}
 182
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