1/* 2 * broadcom blast needs a different resource map 3 * 4 */ 5 6static void setup_blast_resource_map(void) 7{ 8 static const unsigned int register_values[] = { 9 /* Careful set limit registers before base registers which contain the enables */ 10 /* DRAM Limit i Registers 11 * F1:0x44 i = 0 12 * F1:0x4C i = 1 13 * F1:0x54 i = 2 14 * F1:0x5C i = 3 15 * F1:0x64 i = 4 16 * F1:0x6C i = 5 17 * F1:0x74 i = 6 18 * F1:0x7C i = 7 19 * [ 2: 0] Destination Node ID 20 * 000 = Node 0 21 * 001 = Node 1 22 * 010 = Node 2 23 * 011 = Node 3 24 * 100 = Node 4 25 * 101 = Node 5 26 * 110 = Node 6 27 * 111 = Node 7 28 * [ 7: 3] Reserved 29 * [10: 8] Interleave select 30 * specifies the values of A[14:12] to use with interleave enable. 31 * [15:11] Reserved 32 * [31:16] DRAM Limit Address i Bits 39-24 33 * This field defines the upper address bits of a 40 bit address 34 * that define the end of the DRAM region. 35 */ 36 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, 37 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, 38 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, 39 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, 40 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, 41 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, 42 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, 43 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, 44 /* DRAM Base i Registers 45 * F1:0x40 i = 0 46 * F1:0x48 i = 1 47 * F1:0x50 i = 2 48 * F1:0x58 i = 3 49 * F1:0x60 i = 4 50 * F1:0x68 i = 5 51 * F1:0x70 i = 6 52 * F1:0x78 i = 7 53 * [ 0: 0] Read Enable 54 * 0 = Reads Disabled 55 * 1 = Reads Enabled 56 * [ 1: 1] Write Enable 57 * 0 = Writes Disabled 58 * 1 = Writes Enabled 59 * [ 7: 2] Reserved 60 * [10: 8] Interleave Enable 61 * 000 = No interleave 62 * 001 = Interleave on A[12] (2 nodes) 63 * 010 = reserved 64 * 011 = Interleave on A[12] and A[14] (4 nodes) 65 * 100 = reserved 66 * 101 = reserved 67 * 110 = reserved 68 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) 69 * [15:11] Reserved 70 * [13:16] DRAM Base Address i Bits 39-24 71 * This field defines the upper address bits of a 40-bit address 72 * that define the start of the DRAM region. 73 */ 74 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, 75 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, 76 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, 77 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, 78 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, 79 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, 80 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, 81 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, 82 83 /* Memory-Mapped I/O Limit i Registers 84 * F1:0x84 i = 0 85 * F1:0x8C i = 1 86 * F1:0x94 i = 2 87 * F1:0x9C i = 3 88 * F1:0xA4 i = 4 89 * F1:0xAC i = 5 90 * F1:0xB4 i = 6 91 * F1:0xBC i = 7 92 * [ 2: 0] Destination Node ID 93 * 000 = Node 0 94 * 001 = Node 1 95 * 010 = Node 2 96 * 011 = Node 3 97 * 100 = Node 4 98 * 101 = Node 5 99 * 110 = Node 6 100 * 111 = Node 7 101 * [ 3: 3] Reserved 102 * [ 5: 4] Destination Link ID 103 * 00 = Link 0 104 * 01 = Link 1 105 * 10 = Link 2 106 * 11 = Reserved 107 * [ 6: 6] Reserved 108 * [ 7: 7] Non-Posted 109 * 0 = CPU writes may be posted 110 * 1 = CPU writes must be non-posted 111 * [31: 8] Memory-Mapped I/O Limit Address i (39-16) 112 * This field defines the upp adddress bits of a 40-bit address that 113 * defines the end of a memory-mapped I/O region n 114 */ 115 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, 116 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, 117 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, 118 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, 119 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, 120 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, 121 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, 122 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, 123 124 /* Memory-Mapped I/O Base i Registers 125 * F1:0x80 i = 0 126 * F1:0x88 i = 1 127 * F1:0x90 i = 2 128 * F1:0x98 i = 3 129 * F1:0xA0 i = 4 130 * F1:0xA8 i = 5 131 * F1:0xB0 i = 6 132 * F1:0xB8 i = 7 133 * [ 0: 0] Read Enable 134 * 0 = Reads disabled 135 * 1 = Reads Enabled 136 * [ 1: 1] Write Enable 137 * 0 = Writes disabled 138 * 1 = Writes Enabled 139 * [ 2: 2] Cpu Disable 140 * 0 = Cpu can use this I/O range 141 * 1 = Cpu requests do not use this I/O range 142 * [ 3: 3] Lock 143 * 0 = base/limit registers i are read/write 144 * 1 = base/limit registers i are read-only 145 * [ 7: 4] Reserved 146 * [31: 8] Memory-Mapped I/O Base Address i (39-16) 147 * This field defines the upper address bits of a 40bit address 148 * that defines the start of memory-mapped I/O region i 149 */ 150 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, 151 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, 152 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, 153 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, 154 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, 155 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, 156 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, 157 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, 158 159 /* PCI I/O Limit i Registers 160 * F1:0xC4 i = 0 161 * F1:0xCC i = 1 162 * F1:0xD4 i = 2 163 * F1:0xDC i = 3 164 * [ 2: 0] Destination Node ID 165 * 000 = Node 0 166 * 001 = Node 1 167 * 010 = Node 2 168 * 011 = Node 3 169 * 100 = Node 4 170 * 101 = Node 5 171 * 110 = Node 6 172 * 111 = Node 7 173 * [ 3: 3] Reserved 174 * [ 5: 4] Destination Link ID 175 * 00 = Link 0 176 * 01 = Link 1 177 * 10 = Link 2 178 * 11 = reserved 179 * [11: 6] Reserved 180 * [24:12] PCI I/O Limit Address i 181 * This field defines the end of PCI I/O region n 182 * [31:25] Reserved 183 */ 184 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, 185 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 186 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, 187 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, 188 189 /* PCI I/O Base i Registers 190 * F1:0xC0 i = 0 191 * F1:0xC8 i = 1 192 * F1:0xD0 i = 2 193 * F1:0xD8 i = 3 194 * [ 0: 0] Read Enable 195 * 0 = Reads Disabled 196 * 1 = Reads Enabled 197 * [ 1: 1] Write Enable 198 * 0 = Writes Disabled 199 * 1 = Writes Enabled 200 * [ 3: 2] Reserved 201 * [ 4: 4] VGA Enable 202 * 0 = VGA matches Disabled 203 * 1 = matches all address < 64K and where A[9:0] is in the 204 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers 205 * [ 5: 5] ISA Enable 206 * 0 = ISA matches Disabled 207 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block 208 * from matching agains this base/limit pair 209 * [11: 6] Reserved 210 * [24:12] PCI I/O Base i 211 * This field defines the start of PCI I/O region n 212 * [31:25] Reserved 213 */ 214 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, 215 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, 216 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, 217 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, 218 219 /* Config Base and Limit i Registers 220 * F1:0xE0 i = 0 221 * F1:0xE4 i = 1 222 * F1:0xE8 i = 2 223 * F1:0xEC i = 3 224 * [ 0: 0] Read Enable 225 * 0 = Reads Disabled 226 * 1 = Reads Enabled 227 * [ 1: 1] Write Enable 228 * 0 = Writes Disabled 229 * 1 = Writes Enabled 230 * [ 2: 2] Device Number Compare Enable 231 * 0 = The ranges are based on bus number 232 * 1 = The ranges are ranges of devices on bus 0 233 * [ 3: 3] Reserved 234 * [ 6: 4] Destination Node 235 * 000 = Node 0 236 * 001 = Node 1 237 * 010 = Node 2 238 * 011 = Node 3 239 * 100 = Node 4 240 * 101 = Node 5 241 * 110 = Node 6 242 * 111 = Node 7 243 * [ 7: 7] Reserved 244 * [ 9: 8] Destination Link 245 * 00 = Link 0 246 * 01 = Link 1 247 * 10 = Link 2 248 * 11 - Reserved 249 * [15:10] Reserved 250 * [23:16] Bus Number Base i 251 * This field defines the lowest bus number in configuration region i 252 * [31:24] Bus Number Limit i 253 * This field defines the highest bus number in configuration regin i 254 */ 255 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, 256 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 257 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, 258 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 259 }; 260 261 int max; 262 max = ARRAY_SIZE(register_values); 263 setup_resource_map(register_values, max); 264} 265 266