LXR coreboot/src/devices/pci

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
   5 *
   6 * Modifications are:
   7 * Copyright (C) 2003-2004 Linux Networx
   8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
   9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
  10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
  11 * Copyright (C) 2005-2006 Tyan
  12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
  13 * Copyright (C) 2005-2009 coresystems GmbH
  14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
  15 */
  16
  17/*
  18 * PCI Bus Services, see include/linux/pci.h for further explanation.
  19 *
  20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
  21 * David Mosberger-Tang
  22 *
  23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
  24 */
  25
  26#include <console/console.h>
  27#include <stdlib.h>
  28#include <stdint.h>
  29#include <bitops.h>
  30#include <string.h>
  31#include <arch/io.h>
  32#include <device/device.h>
  33#include <device/pci.h>
  34#include <device/pci_ids.h>
  35#include <delay.h>
  36#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
  37#include <device/hypertransport.h>
  38#endif
  39#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
  40#include <device/pcix.h>
  41#endif
  42#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
  43#include <device/pciexp.h>
  44#endif
  45#if CONFIG_AGP_PLUGIN_SUPPORT == 1
  46#include <device/agp.h>
  47#endif
  48#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
  49#include <device/cardbus.h>
  50#endif
  51#if CONFIG_PC80_SYSTEM == 1
  52#include <pc80/i8259.h>
  53#endif
  54
  55u8 pci_moving_config8(struct device *dev, unsigned int reg)
  56{
  57        u8 value, ones, zeroes;
  58
  59        value = pci_read_config8(dev, reg);
  60
  61        pci_write_config8(dev, reg, 0xff);
  62        ones = pci_read_config8(dev, reg);
  63
  64        pci_write_config8(dev, reg, 0x00);
  65        zeroes = pci_read_config8(dev, reg);
  66
  67        pci_write_config8(dev, reg, value);
  68
  69        return ones ^ zeroes;
  70}
  71
  72u16 pci_moving_config16(struct device *dev, unsigned int reg)
  73{
  74        u16 value, ones, zeroes;
  75
  76        value = pci_read_config16(dev, reg);
  77
  78        pci_write_config16(dev, reg, 0xffff);
  79        ones = pci_read_config16(dev, reg);
  80
  81        pci_write_config16(dev, reg, 0x0000);
  82        zeroes = pci_read_config16(dev, reg);
  83
  84        pci_write_config16(dev, reg, value);
  85
  86        return ones ^ zeroes;
  87}
  88
  89u32 pci_moving_config32(struct device *dev, unsigned int reg)
  90{
  91        u32 value, ones, zeroes;
  92
  93        value = pci_read_config32(dev, reg);
  94
  95        pci_write_config32(dev, reg, 0xffffffff);
  96        ones = pci_read_config32(dev, reg);
  97
  98        pci_write_config32(dev, reg, 0x00000000);
  99        zeroes = pci_read_config32(dev, reg);
 100
 101        pci_write_config32(dev, reg, value);
 102
 103        return ones ^ zeroes;
 104}
 105
 106/**
 107 * Given a device, a capability type, and a last position, return the next
 108 * matching capability. Always start at the head of the list.
 109 *
 110 * @param dev Pointer to the device structure.
 111 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
 112 * @param last Location of the PCI capability register to start from.
 113 * @return The next matching capability.
 114 */
 115unsigned pci_find_next_capability(struct device *dev, unsigned cap,
 116                                  unsigned last)
 117{
 118        unsigned pos = 0;
 119        u16 status;
 120        unsigned reps = 48;
 121
 122        status = pci_read_config16(dev, PCI_STATUS);
 123        if (!(status & PCI_STATUS_CAP_LIST))
 124                return 0;
 125
 126        switch (dev->hdr_type & 0x7f) {
 127        case PCI_HEADER_TYPE_NORMAL:
 128        case PCI_HEADER_TYPE_BRIDGE:
 129                pos = PCI_CAPABILITY_LIST;
 130                break;
 131        case PCI_HEADER_TYPE_CARDBUS:
 132                pos = PCI_CB_CAPABILITY_LIST;
 133                break;
 134        default:
 135                return 0;
 136        }
 137
 138        pos = pci_read_config8(dev, pos);
 139        while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
 140                int this_cap;
 141
 142                pos &= ~3;
 143                this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
 144                printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
 145                       this_cap, pos);
 146                if (this_cap == 0xff)
 147                        break;
 148
 149                if (!last && (this_cap == cap))
 150                        return pos;
 151
 152                if (last == pos)
 153                        last = 0;
 154
 155                pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
 156        }
 157        return 0;
 158}
 159
 160/**
 161 * Given a device, and a capability type, return the next matching
 162 * capability. Always start at the head of the list.
 163 *
 164 * @param dev Pointer to the device structure.
 165 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
 166 * @return The next matching capability.
 167 */
 168unsigned pci_find_capability(device_t dev, unsigned cap)
 169{
 170        return pci_find_next_capability(dev, cap, 0);
 171}
 172
 173/**
 174 * Given a device and register, read the size of the BAR for that register.
 175 *
 176 * @param dev Pointer to the device structure.
 177 * @param index Address of the PCI configuration register.
 178 * @return TODO
 179 */
 180struct resource *pci_get_resource(struct device *dev, unsigned long index)
 181{
 182        struct resource *resource;
 183        unsigned long value, attr;
 184        resource_t moving, limit;
 185
 186        /* Initialize the resources to nothing. */
 187        resource = new_resource(dev, index);
 188
 189        /* Get the initial value. */
 190        value = pci_read_config32(dev, index);
 191
 192        /* See which bits move. */
 193        moving = pci_moving_config32(dev, index);
 194
 195        /* Initialize attr to the bits that do not move. */
 196        attr = value & ~moving;
 197
 198        /* If it is a 64bit resource look at the high half as well. */
 199        if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
 200            ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
 201             PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
 202                /* Find the high bits that move. */
 203                moving |=
 204                    ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
 205        }
 206
 207        /* Find the resource constraints.
 208         * Start by finding the bits that move. From there:
 209         * - Size is the least significant bit of the bits that move.
 210         * - Limit is all of the bits that move plus all of the lower bits.
 211         * See PCI Spec 6.2.5.1.
 212         */
 213        limit = 0;
 214        if (moving) {
 215                resource->size = 1;
 216                resource->align = resource->gran = 0;
 217                while (!(moving & resource->size)) {
 218                        resource->size <<= 1;
 219                        resource->align += 1;
 220                        resource->gran += 1;
 221                }
 222                resource->limit = limit = moving | (resource->size - 1);
 223        }
 224
 225        /*
 226         * Some broken hardware has read-only registers that do not
 227         * really size correctly.
 228         *
 229         * Example: the Acer M7229 has BARs 1-4 normally read-only,
 230         * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
 231         * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
 232         * is a violation of the spec.
 233         *
 234         * We catch this case and ignore it by observing which bits move.
 235         *
 236         * This also catches the common case of unimplemented registers
 237         * that always read back as 0.
 238         */
 239        if (moving == 0) {
 240                if (value != 0) {
 241                        printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
 242                               "read-only ignoring it\n",
 243                               dev_path(dev), index, value);
 244                }
 245                resource->flags = 0;
 246        } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
 247                /* An I/O mapped base address. */
 248                attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
 249                resource->flags |= IORESOURCE_IO;
 250                /* I don't want to deal with 32bit I/O resources. */
 251                resource->limit = 0xffff;
 252        } else {
 253                /* A Memory mapped base address. */
 254                attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 255                resource->flags |= IORESOURCE_MEM;
 256                if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
 257                        resource->flags |= IORESOURCE_PREFETCH;
 258                attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
 259                if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
 260                        /* 32bit limit. */
 261                        resource->limit = 0xffffffffUL;
 262                } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
 263                        /* 1MB limit. */
 264                        resource->limit = 0x000fffffUL;
 265                } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
 266                        /* 64bit limit. */
 267                        resource->limit = 0xffffffffffffffffULL;
 268                        resource->flags |= IORESOURCE_PCI64;
 269                } else {
 270                        /* Invalid value. */
 271                        printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
 272                        printk(BIOS_ERR, " on dev %s at index %02lx\n",
 273                               dev_path(dev), index);
 274                        resource->flags = 0;
 275                }
 276        }
 277
 278        /* Don't let the limit exceed which bits can move. */
 279        if (resource->limit > limit)
 280                resource->limit = limit;
 281
 282        return resource;
 283}
 284
 285/**
 286 * Given a device and an index, read the size of the BAR for that register.
 287 *
 288 * @param dev Pointer to the device structure.
 289 * @param index Address of the PCI configuration register.
 290 */
 291static void pci_get_rom_resource(struct device *dev, unsigned long index)
 292{
 293        struct resource *resource;
 294        unsigned long value;
 295        resource_t moving;
 296
 297        /* Initialize the resources to nothing. */
 298        resource = new_resource(dev, index);
 299
 300        /* Get the initial value. */
 301        value = pci_read_config32(dev, index);
 302
 303        /* See which bits move. */
 304        moving = pci_moving_config32(dev, index);
 305
 306        /* Clear the Enable bit. */
 307        moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
 308
 309        /* Find the resource constraints.
 310         * Start by finding the bits that move. From there:
 311         * - Size is the least significant bit of the bits that move.
 312         * - Limit is all of the bits that move plus all of the lower bits.
 313         * See PCI Spec 6.2.5.1.
 314         */
 315        if (moving) {
 316                resource->size = 1;
 317                resource->align = resource->gran = 0;
 318                while (!(moving & resource->size)) {
 319                        resource->size <<= 1;
 320                        resource->align += 1;
 321                        resource->gran += 1;
 322                }
 323                resource->limit = moving | (resource->size - 1);
 324                resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
 325        } else {
 326                if (value != 0) {
 327                        printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
 328                               "read-only ignoring it\n",
 329                               dev_path(dev), index, value);
 330                }
 331                resource->flags = 0;
 332        }
 333        compact_resources(dev);
 334}
 335
 336/**
 337 * Read the base address registers for a given device.
 338 *
 339 * @param dev Pointer to the dev structure.
 340 * @param howmany How many registers to read (6 for device, 2 for bridge).
 341 */
 342static void pci_read_bases(struct device *dev, unsigned int howmany)
 343{
 344        unsigned long index;
 345
 346        for (index = PCI_BASE_ADDRESS_0;
 347             (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
 348                struct resource *resource;
 349                resource = pci_get_resource(dev, index);
 350                index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
 351        }
 352
 353        compact_resources(dev);
 354}
 355
 356static void pci_record_bridge_resource(struct device *dev, resource_t moving,
 357                                       unsigned index, unsigned long type)
 358{
 359        struct resource *resource;
 360        unsigned long gran;
 361        resource_t step;
 362
 363        resource = NULL;
 364
 365        if (!moving)
 366                return;
 367
 368        /* Initialize the constraints on the current bus. */
 369        resource = new_resource(dev, index);
 370        resource->size = 0;
 371        gran = 0;
 372        step = 1;
 373        while ((moving & step) == 0) {
 374                gran += 1;
 375                step <<= 1;
 376        }
 377        resource->gran = gran;
 378        resource->align = gran;
 379        resource->limit = moving | (step - 1);
 380        resource->flags = type | IORESOURCE_PCI_BRIDGE |
 381                          IORESOURCE_BRIDGE;
 382}
 383
 384static void pci_bridge_read_bases(struct device *dev)
 385{
 386        resource_t moving_base, moving_limit, moving;
 387
 388        /* See if the bridge I/O resources are implemented. */
 389        moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
 390        moving_base |=
 391          ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
 392
 393        moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
 394        moving_limit |=
 395          ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
 396
 397        moving = moving_base & moving_limit;
 398
 399        /* Initialize the I/O space constraints on the current bus. */
 400        pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
 401
 402        /* See if the bridge prefmem resources are implemented. */
 403        moving_base =
 404          ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
 405        moving_base |=
 406          ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
 407
 408        moving_limit =
 409          ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
 410        moving_limit |=
 411          ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
 412
 413        moving = moving_base & moving_limit;
 414        /* Initialize the prefetchable memory constraints on the current bus. */
 415        pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
 416                                   IORESOURCE_MEM | IORESOURCE_PREFETCH);
 417
 418        /* See if the bridge mem resources are implemented. */
 419        moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
 420        moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
 421
 422        moving = moving_base & moving_limit;
 423
 424        /* Initialize the memory resources on the current bus. */
 425        pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
 426                                   IORESOURCE_MEM);
 427
 428        compact_resources(dev);
 429}
 430
 431void pci_dev_read_resources(struct device *dev)
 432{
 433        pci_read_bases(dev, 6);
 434        pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
 435}
 436
 437void pci_bus_read_resources(struct device *dev)
 438{
 439        pci_bridge_read_bases(dev);
 440        pci_read_bases(dev, 2);
 441        pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
 442}
 443
 444void pci_domain_read_resources(struct device *dev)
 445{
 446        struct resource *res;
 447
 448        /* Initialize the system-wide I/O space constraints. */
 449        res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 450        res->limit = 0xffffUL;
 451        res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 452                     IORESOURCE_ASSIGNED;
 453
 454        /* Initialize the system-wide memory resources constraints. */
 455        res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 456        res->limit = 0xffffffffULL;
 457        res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 458                     IORESOURCE_ASSIGNED;
 459}
 460
 461static void pci_set_resource(struct device *dev, struct resource *resource)
 462{
 463        resource_t base, end;
 464
 465        /* Make certain the resource has actually been assigned a value. */
 466        if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 467                printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
 468                       "assigned\n", dev_path(dev), resource->index,
 469                       resource_type(resource), resource->size);
 470                return;
 471        }
 472
 473        /* If this resource is fixed don't worry about it. */
 474        if (resource->flags & IORESOURCE_FIXED)
 475                return;
 476
 477        /* If I have already stored this resource don't worry about it. */
 478        if (resource->flags & IORESOURCE_STORED)
 479                return;
 480
 481        /* If the resource is subtractive don't worry about it. */
 482        if (resource->flags & IORESOURCE_SUBTRACTIVE)
 483                return;
 484
 485        /* Only handle PCI memory and I/O resources for now. */
 486        if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 487                return;
 488
 489        /* Enable the resources in the command register. */
 490        if (resource->size) {
 491                if (resource->flags & IORESOURCE_MEM)
 492                        dev->command |= PCI_COMMAND_MEMORY;
 493                if (resource->flags & IORESOURCE_IO)
 494                        dev->command |= PCI_COMMAND_IO;
 495                if (resource->flags & IORESOURCE_PCI_BRIDGE)
 496                        dev->command |= PCI_COMMAND_MASTER;
 497        }
 498
 499        /* Get the base address. */
 500        base = resource->base;
 501
 502        /* Get the end. */
 503        end = resource_end(resource);
 504
 505        /* Now store the resource. */
 506        resource->flags |= IORESOURCE_STORED;
 507
 508        /*
 509         * PCI bridges have no enable bit. They are disabled if the base of
 510         * the range is greater than the limit. If the size is zero, disable
 511         * by setting the base = limit and end = limit - 2^gran.
 512         */
 513        if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
 514                base = resource->limit;
 515                end = resource->limit - (1 << resource->gran);
 516                resource->base = base;
 517        }
 518
 519        if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 520                unsigned long base_lo, base_hi;
 521
 522                /*
 523                 * Some chipsets allow us to set/clear the I/O bit
 524                 * (e.g. VIA 82C686A). So set it to be safe.
 525                 */
 526                base_lo = base & 0xffffffff;
 527                base_hi = (base >> 32) & 0xffffffff;
 528                if (resource->flags & IORESOURCE_IO)
 529                        base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
 530                pci_write_config32(dev, resource->index, base_lo);
 531                if (resource->flags & IORESOURCE_PCI64)
 532                        pci_write_config32(dev, resource->index + 4, base_hi);
 533        } else if (resource->index == PCI_IO_BASE) {
 534                /* Set the I/O ranges. */
 535                pci_write_config8(dev, PCI_IO_BASE, base >> 8);
 536                pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
 537                pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
 538                pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
 539        } else if (resource->index == PCI_MEMORY_BASE) {
 540                /* Set the memory range. */
 541                pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 542                pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
 543        } else if (resource->index == PCI_PREF_MEMORY_BASE) {
 544                /* Set the prefetchable memory range. */
 545                pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
 546                pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
 547                pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
 548                pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
 549        } else {
 550                /* Don't let me think I stored the resource. */
 551                resource->flags &= ~IORESOURCE_STORED;
 552                printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
 553                       resource->index);
 554        }
 555
 556        report_resource_stored(dev, resource, "");
 557}
 558
 559void pci_dev_set_resources(struct device *dev)
 560{
 561        struct resource *res;
 562        struct bus *bus;
 563        u8 line;
 564
 565        for (res = dev->resource_list; res; res = res->next)
 566                pci_set_resource(dev, res);
 567
 568        for (bus = dev->link_list; bus; bus = bus->next) {
 569                if (bus->children)
 570                        assign_resources(bus);
 571        }
 572
 573        /* Set a default latency timer. */
 574        pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 575
 576        /* Set a default secondary latency timer. */
 577        if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
 578                pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
 579
 580        /* Zero the IRQ settings. */
 581        line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 582        if (line)
 583                pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 584
 585        /* Set the cache line size, so far 64 bytes is good for everyone. */
 586        pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 587}
 588
 589void pci_dev_enable_resources(struct device *dev)
 590{
 591        const struct pci_operations *ops;
 592        u16 command;
 593
 594        /* Set the subsystem vendor and device ID for mainboard devices. */
 595        ops = ops_pci(dev);
 596        if (dev->on_mainboard && ops && ops->set_subsystem) {
 597                printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
 598                        dev_path(dev), dev->subsystem_vendor,
 599                        dev->subsystem_device);
 600                ops->set_subsystem(dev, dev->subsystem_vendor,
 601                        dev->subsystem_device);
 602        }
 603        command = pci_read_config16(dev, PCI_COMMAND);
 604        command |= dev->command;
 605
 606        /* v3 has
 607         * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR);  // Error check.
 608         */
 609
 610        printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 611        pci_write_config16(dev, PCI_COMMAND, command);
 612}
 613
 614void pci_bus_enable_resources(struct device *dev)
 615{
 616        u16 ctrl;
 617
 618        /*
 619         * Enable I/O in command register if there is VGA card
 620         * connected with (even it does not claim I/O resource).
 621         */
 622        if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
 623                dev->command |= PCI_COMMAND_IO;
 624        ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 625        ctrl |= dev->link_list->bridge_ctrl;
 626        ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
 627        printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 628        pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 629
 630        pci_dev_enable_resources(dev);
 631}
 632
 633void pci_bus_reset(struct bus *bus)
 634{
 635        u16 ctl;
 636
 637        ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
 638        ctl |= PCI_BRIDGE_CTL_BUS_RESET;
 639        pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
 640        mdelay(10);
 641
 642        ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 643        pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
 644        delay(1);
 645}
 646
 647void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 648{
 649        pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 650                           ((device & 0xffff) << 16) | (vendor & 0xffff));
 651}
 652
 653/** Default handler: only runs the relevant PCI BIOS. */
 654void pci_dev_init(struct device *dev)
 655{
 656#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
 657        struct rom_header *rom, *ram;
 658
 659        if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
 660            ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
 661                return;
 662
 663        if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
 664            ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
 665                return;
 666
 667        rom = pci_rom_probe(dev);
 668        if (rom == NULL)
 669                return;
 670
 671        ram = pci_rom_load(dev, rom);
 672        if (ram == NULL)
 673                return;
 674
 675        run_bios(dev, (unsigned long)ram);
 676#endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
 677}
 678
 679/** Default device operation for PCI devices */
 680static struct pci_operations pci_dev_ops_pci = {
 681        .set_subsystem = pci_dev_set_subsystem,
 682};
 683
 684struct device_operations default_pci_ops_dev = {
 685        .read_resources   = pci_dev_read_resources,
 686        .set_resources    = pci_dev_set_resources,
 687        .enable_resources = pci_dev_enable_resources,
 688        .init             = pci_dev_init,
 689        .scan_bus         = 0,
 690        .enable           = 0,
 691        .ops_pci          = &pci_dev_ops_pci,
 692};
 693
 694/** Default device operations for PCI bridges */
 695static struct pci_operations pci_bus_ops_pci = {
 696        .set_subsystem = 0,
 697};
 698
 699struct device_operations default_pci_ops_bus = {
 700        .read_resources   = pci_bus_read_resources,
 701        .set_resources    = pci_dev_set_resources,
 702        .enable_resources = pci_bus_enable_resources,
 703        .init             = 0,
 704        .scan_bus         = pci_scan_bridge,
 705        .enable           = 0,
 706        .reset_bus        = pci_bus_reset,
 707        .ops_pci          = &pci_bus_ops_pci,
 708};
 709
 710/**
 711 * Detect the type of downstream bridge.
 712 *
 713 * This function is a heuristic to detect which type of bus is downstream
 714 * of a PCI-to-PCI bridge. This functions by looking for various capability
 715 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
 716 * Hypertransport all seem to have appropriate capabilities.
 717 *
 718 * When only a PCI-Express capability is found the type is examined to see
 719 * which type of bridge we have.
 720 *
 721 * @param dev Pointer to the device structure of the bridge.
 722 * @return Appropriate bridge operations.
 723 */
 724static struct device_operations *get_pci_bridge_ops(device_t dev)
 725{
 726        unsigned int pos;
 727
 728#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
 729        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 730        if (pos) {
 731                printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
 732                return &default_pcix_ops_bus;
 733        }
 734#endif
 735#if CONFIG_AGP_PLUGIN_SUPPORT == 1
 736        /* How do I detect a PCI to AGP bridge? */
 737#endif
 738#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
 739        pos = 0;
 740        while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
 741                u16 flags;
 742                flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 743                if ((flags >> 13) == 1) {
 744                        /* Host or Secondary Interface */
 745                        printk(BIOS_DEBUG, "%s subordinate bus HT\n",
 746                               dev_path(dev));
 747                        return &default_ht_ops_bus;
 748                }
 749        }
 750#endif
 751#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
 752        pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 753        if (pos) {
 754                u16 flags;
 755                flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
 756                switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
 757                case PCI_EXP_TYPE_ROOT_PORT:
 758                case PCI_EXP_TYPE_UPSTREAM:
 759                case PCI_EXP_TYPE_DOWNSTREAM:
 760                        printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
 761                               dev_path(dev));
 762                        return &default_pciexp_ops_bus;
 763                case PCI_EXP_TYPE_PCI_BRIDGE:
 764                        printk(BIOS_DEBUG, "%s subordinate PCI\n",
 765                               dev_path(dev));
 766                        return &default_pci_ops_bus;
 767                default:
 768                        break;
 769                }
 770        }
 771#endif
 772        return &default_pci_ops_bus;
 773}
 774
 775/**
 776 * Set up PCI device operation.
 777 *
 778 * Check if it already has a driver. If not, use find_device_operations(),
 779 * or set to a default based on type.
 780 *
 781 * @param dev Pointer to the device whose pci_ops you want to set.
 782 * @see pci_drivers
 783 */
 784static void set_pci_ops(struct device *dev)
 785{
 786        struct pci_driver *driver;
 787
 788        if (dev->ops)
 789                return;
 790
 791        /*
 792         * Look through the list of setup drivers and find one for
 793         * this PCI device.
 794         */
 795        for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
 796                if ((driver->vendor == dev->vendor) &&
 797                    (driver->device == dev->device)) {
 798                        dev->ops = (struct device_operations *)driver->ops;
 799                        printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
 800                               dev_path(dev), driver->vendor, driver->device,
 801                               (driver->ops->scan_bus ? "bus " : ""));
 802                        return;
 803                }
 804        }
 805
 806        /* If I don't have a specific driver use the default operations. */
 807        switch (dev->hdr_type & 0x7f) { /* Header type */
 808        case PCI_HEADER_TYPE_NORMAL:
 809                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 810                        goto bad;
 811                dev->ops = &default_pci_ops_dev;
 812                break;
 813        case PCI_HEADER_TYPE_BRIDGE:
 814                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 815                        goto bad;
 816                dev->ops = get_pci_bridge_ops(dev);
 817                break;
 818#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
 819        case PCI_HEADER_TYPE_CARDBUS:
 820                dev->ops = &default_cardbus_ops_bus;
 821                break;
 822#endif
 823default:
 824bad:
 825                if (dev->enabled) {
 826                        printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
 827                               "header type %02x, ignoring.\n", dev_path(dev),
 828                               dev->vendor, dev->device,
 829                               dev->class >> 8, dev->hdr_type);
 830                }
 831        }
 832}
 833
 834/**
 835 * See if we have already allocated a device structure for a given devfn.
 836 *
 837 * Given a linked list of PCI device structures and a devfn number, find the
 838 * device structure correspond to the devfn, if present. This function also
 839 * removes the device structure from the linked list.
 840 *
 841 * @param list The device structure list.
 842 * @param devfn A device/function number.
 843 * @return Pointer to the device structure found or NULL if we have not
 844 *         allocated a device for this devfn yet.
 845 */
 846static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
 847{
 848        struct device *dev;
 849
 850        dev = 0;
 851        for (; *list; list = &(*list)->sibling) {
 852                if ((*list)->path.type != DEVICE_PATH_PCI) {
 853                        printk(BIOS_ERR, "child %s not a PCI device\n",
 854                               dev_path(*list));
 855                        continue;
 856                }
 857                if ((*list)->path.pci.devfn == devfn) {
 858                        /* Unlink from the list. */
 859                        dev = *list;
 860                        *list = (*list)->sibling;
 861                        dev->sibling = NULL;
 862                        break;
 863                }
 864        }
 865
 866        /*
 867         * Just like alloc_dev() add the device to the list of devices on the
 868         * bus. When the list of devices was formed we removed all of the
 869         * parents children, and now we are interleaving static and dynamic
 870         * devices in order on the bus.
 871         */
 872        if (dev) {
 873                struct device *child;
 874
 875                /* Find the last child of our parent. */
 876                for (child = dev->bus->children; child && child->sibling;)
 877                        child = child->sibling;
 878
 879                /* Place the device on the list of children of its parent. */
 880                if (child)
 881                        child->sibling = dev;
 882                else
 883                        dev->bus->children = dev;
 884        }
 885
 886        return dev;
 887}
 888
 889/**
 890 * Scan a PCI bus.
 891 *
 892 * Determine the existence of a given PCI device. Allocate a new struct device
 893 * if dev==NULL was passed in and the device exists in hardware.
 894 *
 895 * @param dev Pointer to the dev structure.
 896 * @param bus Pointer to the bus structure.
 897 * @param devfn A device/function number to look at.
 898 * @return The device structure for the device (if found), NULL otherwise.
 899 */
 900device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
 901{
 902        u32 id, class;
 903        u8 hdr_type;
 904
 905        /* Detect if a device is present. */
 906        if (!dev) {
 907                struct device dummy;
 908
 909                dummy.bus = bus;
 910                dummy.path.type = DEVICE_PATH_PCI;
 911                dummy.path.pci.devfn = devfn;
 912
 913                id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 914                /*
 915                 * Have we found something? Some broken boards return 0 if a
 916                 * slot is empty, but the expected answer is 0xffffffff.
 917                 */
 918                if (id == 0xffffffff)
 919                        return NULL;
 920
 921                if ((id == 0x00000000) || (id == 0x0000ffff) ||
 922                    (id == 0xffff0000)) {
 923                        printk(BIOS_SPEW, "%s, bad id 0x%x\n",
 924                               dev_path(&dummy), id);
 925                        return NULL;
 926                }
 927                dev = alloc_dev(bus, &dummy.path);
 928        } else {
 929                /*
 930                 * Enable/disable the device. Once we have found the device-
 931                 * specific operations this operations we will disable the
 932                 * device with those as well.
 933                 *
 934                 * This is geared toward devices that have subfunctions
 935                 * that do not show up by default.
 936                 *
 937                 * If a device is a stuff option on the motherboard
 938                 * it may be absent and enable_dev() must cope.
 939                 */
 940                /* Run the magic enable sequence for the device. */
 941                if (dev->chip_ops && dev->chip_ops->enable_dev)
 942                        dev->chip_ops->enable_dev(dev);
 943
 944                /* Now read the vendor and device ID. */
 945                id = pci_read_config32(dev, PCI_VENDOR_ID);
 946
 947                /*
 948                 * If the device does not have a PCI ID disable it. Possibly
 949                 * this is because we have already disabled the device. But
 950                 * this also handles optional devices that may not always
 951                 * show up.
 952                 */
 953                /* If the chain is fully enumerated quit */
 954                if ((id == 0xffffffff) || (id == 0x00000000) ||
 955                    (id == 0x0000ffff) || (id == 0xffff0000)) {
 956                        if (dev->enabled) {
 957                                printk(BIOS_INFO, "PCI: Static device %s not "
 958                                       "found, disabling it.\n", dev_path(dev));
 959                                dev->enabled = 0;
 960                        }
 961                        return dev;
 962                }
 963        }
 964
 965        /* Read the rest of the PCI configuration information. */
 966        hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 967        class = pci_read_config32(dev, PCI_CLASS_REVISION);
 968
 969        /* Store the interesting information in the device structure. */
 970        dev->vendor = id & 0xffff;
 971        dev->device = (id >> 16) & 0xffff;
 972        dev->hdr_type = hdr_type;
 973
 974        /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
 975        dev->class = class >> 8;
 976
 977        /* Architectural/System devices always need to be bus masters. */
 978        if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
 979                dev->command |= PCI_COMMAND_MASTER;
 980
 981        /*
 982         * Look at the vendor and device ID, or at least the header type and
 983         * class and figure out which set of configuration methods to use.
 984         * Unless we already have some PCI ops.
 985         */
 986        set_pci_ops(dev);
 987
 988        /* Now run the magic enable/disable sequence for the device. */
 989        if (dev->ops && dev->ops->enable)
 990                dev->ops->enable(dev);
 991
 992        /* Display the device. */
 993        printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
 994               dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
 995               dev->ops ? "" : " No operations");
 996
 997        return dev;
 998}
 999
1000/**

1001 * Scan a PCI bus.
1002 *
1003 * Determine the existence of devices and bridges on a PCI bus. If there are
1004 * bridges on the bus, recursively scan the buses behind the bridges.
1005 *
1006 * This function is the default scan_bus() method for the root device
1007 * 'dev_root'.
1008 *
1009 * @param bus Pointer to the bus structure.
1010 * @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
1011 * @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
1012 * @param max Current bus number.
1013 * @return The maximum bus number found, after scanning all subordinate busses.
1014 */
1015unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
1016                          unsigned max_devfn, unsigned int max)
1017{
1018        unsigned int devfn;
1019        struct device *old_devices;
1020        struct device *child;
1021
1022#if CONFIG_PCI_BUS_SEGN_BITS
1023        printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1024               bus->secondary >> 8, bus->secondary & 0xff);
1025#else
1026        printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1027#endif
1028
1029        /* Maximum sane devfn is 0xFF. */
1030        if (max_devfn > 0xff) {
1031                printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
1032                       "devfn %x\n", min_devfn, max_devfn);
1033                printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
1034                       "Using 0xff.\n");
1035                max_devfn=0xff;
1036        }
1037
1038        old_devices = bus->children;
1039        bus->children = NULL;
1040
1041        post_code(0x24);
1042
1043        /*
1044         * Probe all devices/functions on this bus with some optimization for
1045         * non-existence and single function devices.
1046         */
1047        for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1048                struct device *dev;
1049
1050                /* First thing setup the device structure. */
1051                dev = pci_scan_get_dev(&old_devices, devfn);
1052
1053                /* See if a device is present and setup the device structure. */
1054                dev = pci_probe_dev(dev, bus, devfn);
1055
1056                /*
1057                 * If this is not a multi function device, or the device is
1058                 * not present don't waste time probing another function.
1059                 * Skip to next device.
1060                 */
1061                if ((PCI_FUNC(devfn) == 0x00) && (!dev
1062                     || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1063                        devfn += 0x07;
1064                }
1065        }
1066
1067        post_code(0x25);
1068
1069        /*
1070         * Warn if any leftover static devices are are found.
1071         * There's probably a problem in devicetree.cb.
1072         */
1073        if (old_devices) {
1074                device_t left;
1075                printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1076                for (left = old_devices; left; left = left->sibling)
1077                        printk(BIOS_WARNING, "%s\n", dev_path(left));
1078
1079                printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
1080        }
1081
1082        /*
1083         * For all children that implement scan_bus() (i.e. bridges)
1084         * scan the bus behind that child.
1085         */
1086        for (child = bus->children; child; child = child->sibling)
1087                max = scan_bus(child, max);
1088
1089        /*
1090         * We've scanned the bus and so we know all about what's on the other
1091         * side of any bridges that may be on this bus plus any devices.
1092         * Return how far we've got finding sub-buses.
1093         */
1094        printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1095        post_code(0x55);
1096        return max;
1097}
1098
1099/**
1100 * Scan a PCI bridge and the buses behind the bridge.
1101 *
1102 * Determine the existence of buses behind the bridge. Set up the bridge
1103 * according to the result of the scan.
1104 *
1105 * This function is the default scan_bus() method for PCI bridge devices.
1106 *
1107 * @param dev Pointer to the bridge device.
1108 * @param max The highest bus number assigned up to now.
1109 * @param do_scan_bus TODO
1110 * @return The maximum bus number found, after scanning all subordinate buses.
1111 */
1112unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1113                                unsigned int (*do_scan_bus) (struct bus * bus,
1114                                                             unsigned min_devfn,
1115                                                             unsigned max_devfn,
1116                                                             unsigned int max))
1117{
1118        struct bus *bus;
1119        u32 buses;
1120        u16 cr;
1121
1122        printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1123
1124        if (dev->link_list == NULL) {
1125                struct bus *link;
1126                link = malloc(sizeof(*link));
1127                if (link == NULL)
1128                        die("Couldn't allocate a link!\n");
1129                memset(link, 0, sizeof(*link));
1130                link->dev = dev;
1131                dev->link_list = link;
1132        }
1133
1134        bus = dev->link_list;
1135
1136        /*
1137         * Set up the primary, secondary and subordinate bus numbers. We have
1138         * no idea how many buses are behind this bridge yet, so we set the
1139         * subordinate bus number to 0xff for the moment.
1140         */
1141        bus->secondary = ++max;
1142        bus->subordinate = 0xff;
1143
1144        /* Clear all status bits and turn off memory, I/O and master enables. */
1145        cr = pci_read_config16(dev, PCI_COMMAND);
1146        pci_write_config16(dev, PCI_COMMAND, 0x0000);
1147        pci_write_config16(dev, PCI_STATUS, 0xffff);
1148
1149        /*
1150         * Read the existing primary/secondary/subordinate bus
1151         * number configuration.
1152         */
1153        buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1154
1155        /*
1156         * Configure the bus numbers for this bridge: the configuration
1157         * transactions will not be propagated by the bridge if it is not
1158         * correctly configured.
1159         */
1160        buses &= 0xff000000;
1161        buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1162                  ((unsigned int)(bus->secondary) << 8) |
1163                  ((unsigned int)(bus->subordinate) << 16));
1164        pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1165
1166        /* Now we can scan all subordinate buses (those behind the bridge). */
1167        max = do_scan_bus(bus, 0x00, 0xff, max);
1168
1169        /*
1170         * We know the number of buses behind this bridge. Set the subordinate
1171         * bus number to its real value.
1172         */
1173        bus->subordinate = max;
1174        buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1175        pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1176        pci_write_config16(dev, PCI_COMMAND, cr);
1177
1178        printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1179        return max;
1180}
1181
1182/**
1183 * Scan a PCI bridge and the buses behind the bridge.
1184 *
1185 * Determine the existence of buses behind the bridge. Set up the bridge
1186 * according to the result of the scan.
1187 *
1188 * This function is the default scan_bus() method for PCI bridge devices.
1189 *
1190 * @param dev Pointer to the bridge device.
1191 * @param max The highest bus number assigned up to now.
1192 * @return The maximum bus number found, after scanning all subordinate buses.
1193 */
1194unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1195{
1196        return do_pci_scan_bridge(dev, max, pci_scan_bus);
1197}
1198
1199/**
1200 * Scan a PCI domain.
1201 *
1202 * This function is the default scan_bus() method for PCI domains.
1203 *
1204 * @param dev Pointer to the domain.
1205 * @param max The highest bus number assigned up to now.
1206 * @return The maximum bus number found, after scanning all subordinate busses.
1207 */
1208unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1209{
1210        max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
1211        return max;
1212}
1213
1214#if CONFIG_PC80_SYSTEM == 1
1215/**
1216 * Assign IRQ numbers.
1217 *
1218 * This function assigns IRQs for all functions contained within the indicated
1219 * device address. If the device does not exist or does not require interrupts
1220 * then this function has no effect.
1221 *
1222 * This function should be called for each PCI slot in your system.
1223 *
1224 * @param bus Pointer to the bus structure.
1225 * @param slot TODO
1226 * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD
1227 *        of this slot. The particular IRQ #s that are passed in depend on the
1228 *        routing inside your southbridge and on your board.
1229 */
1230void pci_assign_irqs(unsigned bus, unsigned slot,
1231                     const unsigned char pIntAtoD[4])
1232{
1233        unsigned int funct;
1234        device_t pdev;
1235        u8 line, irq;
1236
1237        /* Each slot may contain up to eight functions. */
1238        for (funct = 0; funct < 8; funct++) {
1239                pdev = dev_find_slot(bus, (slot << 3) + funct);
1240
1241                if (!pdev)
1242                        continue;
1243
1244                line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1245
1246                /* PCI spec says all values except 1..4 are reserved. */
1247                if ((line < 1) || (line > 4))
1248                        continue;
1249
1250                irq = pIntAtoD[line - 1];
1251
1252                printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1253                       irq, bus, slot, funct);
1254
1255                pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1256                                  pIntAtoD[line - 1]);
1257
1258#ifdef PARANOID_IRQ_ASSIGNMENTS
1259                irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1260                printk(BIOS_DEBUG, "  Readback = %d\n", irq);
1261#endif
1262
1263#if CONFIG_PC80_SYSTEM == 1
1264                /* Change to level triggered. */
1265                i8259_configure_irq_trigger(pIntAtoD[line - 1],
1266                                            IRQ_LEVEL_TRIGGERED);
1267#endif
1268        }
1269}
1270#endif
1271