LXR coreboot/src/mainboard/ibm/e326/mptable.c

   1#include <console/console.h>
   2#include <arch/smp/mpspec.h>
   3#include <arch/ioapic.h>
   4#include <device/pci.h>
   5#include <string.h>
   6#include <stdint.h>
   7
   8static void *smp_write_config_table(void *v)
   9{
  10        struct mp_config_table *mc;
  11
  12        int bus_isa;
  13        unsigned char bus_8111_0;
  14        unsigned char bus_8111_1;
  15        unsigned char bus_8131_1;
  16        unsigned char bus_8131_2;
  17
  18        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  19
  20        mptable_init(mc, LAPIC_ADDR);
  21
  22        smp_write_processors(mc);
  23
  24        {
  25                device_t dev;
  26
  27                /* 8111 */
  28                dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
  29                if (dev) {
  30                        bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
  31                        bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  32                } else {
  33                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
  34                        bus_8111_0 = 1;
  35                        bus_8111_1 = 4;
  36                }
  37
  38                /* 8131-1 */
  39                dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
  40                if (dev) {
  41                        bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  42                } else {
  43                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
  44                        bus_8131_1 = 2;
  45                }
  46
  47                /* 8131-2 */
  48                dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
  49                if (dev) {
  50                        bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  51                } else {
  52                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  53                        bus_8131_2 = 3;
  54                }
  55        }
  56
  57        mptable_write_buses(mc, NULL, &bus_isa);
  58
  59        /* Legacy IOAPIC #2 */
  60        smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
  61        {
  62                device_t dev;
  63                struct resource *res;
  64                /* 8131-1 apic #3 */
  65                dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
  66                if (dev) {
  67                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
  68                        if (res) {
  69                                smp_write_ioapic(mc, 0x03, 0x11, res->base);
  70                        }
  71                }
  72                /* 8131-2 apic #4 */
  73                dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
  74                if (dev) {
  75                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
  76                        if (res) {
  77                                smp_write_ioapic(mc, 0x04, 0x11, res->base);
  78                        }
  79                }
  80        }
  81
  82        mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
  83
  84        /* PCI Ints:         Type       Polarity            Trigger                     Bus ID      PCIDEVNUM|IRQ  APIC ID PIN# */
  85        /* Integrated SMBus 2.0 */
  86        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
  87        /* Integrated AMD AC97 Audio */
  88        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
  89
  90        /* Integrated AMD USB */
  91        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
  92
  93        /* On board ATI Rage XL */
  94        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
  95
  96        /* On board Broadcom nics */
  97        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
  98        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
  99
 100        /* On board LSI SCSI */
 101        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
 102
 103        /* PCI Slot 1 PCIX */
 104        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
 105        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
 106        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
 107        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
 108
 109        /* PCI Slot 2 PCIX */
 110        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
 111        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
 112        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
 113        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
 114
 115        /* Standard local interrupt assignments:
 116         *                    Type       Polarity               Trigger                  Bus ID   IRQ   APIC ID      PIN# */
 117        smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
 118        smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
 119
 120        /* There is no extension information... */
 121
 122        /* Compute the checksums */
 123        mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 124        mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 125        printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 126                     mc, smp_next_mpe_entry(mc));
 127        return smp_next_mpe_entry(mc);
 128}
 129
 130unsigned long write_smp_table(unsigned long addr)
 131{
 132        void *v;
 133        v = smp_write_floating_table(addr);
 134        return (unsigned long)smp_write_config_table(v);
 135}
 136
 137