1#include <arch/pirq_routing.h>
2#include <device/pci.h>
3
4#define IRQ_ROUTER_BUS 1
5#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
6#define IRQ_ROUTER_VENDOR 0x1022
7#define IRQ_ROUTER_DEVICE 0x746b
8
9#define AVAILABLE_IRQS 0xdef8
10#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
11 { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
12 {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
13
14
15
16
17
18const struct irq_routing_table intel_irq_routing_table = {
19 PIRQ_SIGNATURE,
20 PIRQ_VERSION,
21 32+16*CONFIG_IRQ_SLOT_COUNT,
22 IRQ_ROUTER_BUS,
23 IRQ_ROUTER_DEVFN,
24 0x00,
25 IRQ_ROUTER_VENDOR,
26 IRQ_ROUTER_DEVICE,
27 0x00,
28 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
29 0xb0,
30 {
31
32 IRQ_SLOT(1, 3,1,0, 2,3,4,1 ),
33 IRQ_SLOT(2, 3,2,0, 3,4,1,2 ),
34 IRQ_SLOT(3, 2,1,0, 2,3,4,1 ),
35 IRQ_SLOT(4, 2,2,0, 3,4,1,2 ),
36 IRQ_SLOT(5, 4,5,0, 2,3,4,1 ),
37 IRQ_SLOT(6, 4,4,0, 1,2,3,4 ),
38
39 IRQ_SLOT(0, 2,3,0, 4,0,0,0 ),
40 IRQ_SLOT(0, 2,4,0, 4,0,0,0 ),
41
42 IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
43 }
44};
45unsigned long write_pirq_routing_table(unsigned long addr)
46{
47 return copy_pirq_routing_table(addr);
48}
49