LXR coreboot/src/drivers/oxford/oxpcie/Kconfig

   1config DRIVERS_OXFORD_OXPCIE
   2        bool "Oxford OXPCIe952"
   3        default n
   4        select HAVE_UART_MEMORY_MAPPED
   5        help
   6          Support for Oxford OXPCIe952 serial port PCIe cards.
   7          Currently only devices with the vendor ID 0x1415 and device ID
   8          0xc158 will work.
   9          NOTE: Right now you have to set the base address of your OXPCIe952
  10          card to exactly the value that the device allocator would set them
  11          later on, or serial console functionality will stop as soon as the
  12          resource allocator assigns a new base address to the device.
  13
  14config OXFORD_OXPCIE_BRIDGE_BUS
  15        hex "OXPCIe's PCIe bridge bus number"
  16        default 0x0
  17        depends on DRIVERS_OXFORD_OXPCIE
  18        help
  19          While coreboot is executing code from ROM, the coreboot resource
  20          allocator has not been running yet. Hence PCI devices living behind
  21          a bridge are not yet visible to the system. In order to use an
  22          OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
  23          that controls the OXPCIe952 controller first.
  24
  25config OXFORD_OXPCIE_BRIDGE_DEVICE
  26        hex "OXPCIe's PCIe bridge device number"
  27        default 0x1c
  28        depends on DRIVERS_OXFORD_OXPCIE
  29        help
  30          While coreboot is executing code from ROM, the coreboot resource
  31          allocator has not been running yet. Hence PCI devices living behind
  32          a bridge are not yet visible to the system. In order to use an
  33          OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
  34          that controls the OXPCIe952 controller first.
  35
  36config OXFORD_OXPCIE_BRIDGE_FUNCTION
  37        hex "OXPCIe's PCIe bridge function number"
  38        default 0x2
  39        depends on DRIVERS_OXFORD_OXPCIE
  40        help
  41          While coreboot is executing code from ROM, the coreboot resource
  42          allocator has not been running yet. Hence PCI devices living behind
  43          a bridge are not yet visible to the system. In order to use an
  44          OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
  45          that controls the OXPCIe952 controller first.
  46
  47config OXFORD_OXPCIE_BRIDGE_SUBORDINATE
  48        hex "OXPCIe's PCIe bridge subordinate bus"
  49        default 0x3
  50        depends on DRIVERS_OXFORD_OXPCIE
  51        help
  52          While coreboot is executing code from ROM, the coreboot resource
  53          allocator has not been running yet. Hence PCI devices living behind
  54          a bridge are not yet visible to the system. In order to use an
  55          OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
  56          that controls the OXPCIe952 controller first.
  57
  58config OXFORD_OXPCIE_BASE_ADDRESS
  59        hex "Base address for rom stage console"
  60        default 0xe0400000
  61        depends on DRIVERS_OXFORD_OXPCIE
  62        help
  63          While coreboot is executing code from ROM, the coreboot resource
  64          allocator has not been running yet. Hence PCI devices living behind
  65          a bridge are not yet visible to the system. In order to use an
  66          OXPCIe952 based PCIe card, coreboot has to set up a temporary address
  67          for the OXPCIe952 controller.
  68
  69