coreboot/src/Kconfig
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   1##
   2## This file is part of the coreboot project.
   3##
   4## Copyright (C) 2009-2010 coresystems GmbH
   5##
   6## This program is free software; you can redistribute it and/or modify
   7## it under the terms of the GNU General Public License as published by
   8## the Free Software Foundation; version 2 of the License.
   9##
  10## This program is distributed in the hope that it will be useful,
  11## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13## GNU General Public License for more details.
  14##
  15## You should have received a copy of the GNU General Public License
  16## along with this program; if not, write to the Free Software
  17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18##
  19
  20mainmenu "Coreboot Configuration"
  21
  22menu "General setup"
  23
  24config EXPERT
  25        bool "Expert mode"
  26        help
  27          This allows you to select certain advanced configuration options.
  28
  29          Warning: Only enable this option if you really know what you are
  30          doing! You have been warned!
  31
  32config LOCALVERSION
  33        string "Local version string"
  34        help
  35          Append an extra string to the end of the coreboot version.
  36
  37          This can be useful if, for instance, you want to append the
  38          respective board's hostname or some other identifying string to
  39          the coreboot version number, so that you can easily distinguish
  40          boot logs of different boards from each other.
  41
  42config CBFS_PREFIX
  43        string "CBFS prefix to use"
  44        default "fallback"
  45        help
  46          Select the prefix to all files put into the image. It's "fallback"
  47          by default, "normal" is a common alternative.
  48
  49choice
  50        prompt "Compiler"
  51        default COMPILER_GCC
  52        help
  53          This option allows you to select the compiler used for building
  54          coreboot.
  55
  56config COMPILER_GCC
  57        bool "GCC"
  58config COMPILER_LLVM_CLANG
  59        bool "LLVM/clang"
  60endchoice
  61
  62config SCANBUILD_ENABLE
  63        bool "Build with scan-build for static analysis"
  64        default n
  65        help
  66          Changes the build process to scan-build is used.
  67          Requires scan-build in path.
  68
  69config SCANBUILD_REPORT_LOCATION
  70        string "Directory to put scan-build report in"
  71        default ""
  72        depends on SCANBUILD_ENABLE
  73        help
  74          Where the scan-build report should be stored
  75
  76config CCACHE
  77        bool "ccache"
  78        default n
  79        help
  80          Enables the use of ccache for faster builds.
  81          Requires ccache in path.
  82
  83config SCONFIG_GENPARSER
  84        bool "Generate SCONFIG parser using flex and bison"
  85        default n
  86        depends on EXPERT
  87        help
  88          Enable this option if you are working on the sconfig
  89          device tree parser and made changes to sconfig.l and
  90          sconfig.y. 
  91          Otherwise, say N.
  92
  93config USE_OPTION_TABLE
  94        bool "Use CMOS for configuration values"
  95        default n
  96        depends on HAVE_OPTION_TABLE
  97        help
  98          Enable this option if coreboot shall read options from the "CMOS"
  99          NVRAM instead of using hard coded values.
 100
 101config COMPRESS_RAMSTAGE
 102        bool "Compress ramstage with LZMA"
 103        default y
 104        help
 105          Compress ramstage to save memory in the flash image. Note
 106          that decompression might slow down booting if the boot flash
 107          is connected through a slow Link (i.e. SPI)
 108
 109endmenu
 110
 111source src/mainboard/Kconfig
 112
 113# This option is used to set the architecture of a mainboard to X86.
 114# It is usually set in mainboard/*/Kconfig.
 115config ARCH_X86
 116        bool
 117        default n
 118
 119if ARCH_X86
 120source src/arch/x86/Kconfig
 121endif
 122
 123menu "Chipset"
 124
 125comment "CPU"
 126source src/cpu/Kconfig
 127comment "Northbridge"
 128source src/northbridge/Kconfig
 129comment "Southbridge"
 130source src/southbridge/Kconfig
 131comment "Super I/O"
 132source src/superio/Kconfig
 133comment "Devices"
 134source src/devices/Kconfig
 135comment "Embedded Controllers"
 136source src/ec/Kconfig
 137
 138endmenu
 139
 140menu "Generic Drivers"
 141source src/drivers/Kconfig
 142endmenu
 143
 144config PCI_BUS_SEGN_BITS
 145        int
 146        default 0
 147
 148config PCI_ROM_RUN
 149        bool
 150        default n
 151
 152config HEAP_SIZE
 153        hex
 154        default 0x4000
 155
 156config MAX_CPUS
 157        int
 158        default 1
 159
 160config MMCONF_SUPPORT_DEFAULT
 161        bool
 162        default n
 163
 164config MMCONF_SUPPORT
 165        bool
 166        default n
 167
 168source src/console/Kconfig
 169
 170# This should default to N and be set by SuperI/O drivers that have an UART
 171config HAVE_UART_IO_MAPPED
 172        bool
 173        default y
 174
 175config HAVE_UART_MEMORY_MAPPED
 176        bool
 177        default n
 178
 179config HAVE_ACPI_RESUME
 180        bool
 181        default n
 182
 183config HAVE_ACPI_SLIC
 184        bool
 185        default n
 186
 187config ACPI_SSDTX_NUM
 188        int
 189        default 0
 190
 191config HAVE_HARD_RESET
 192        bool
 193        default y if BOARD_HAS_HARD_RESET
 194        default n
 195        help
 196          This variable specifies whether a given board has a hard_reset
 197          function, no matter if it's provided by board code or chipset code.
 198
 199config HAVE_INIT_TIMER
 200        bool
 201        default n if UDELAY_IO
 202        default y
 203
 204config HAVE_MAINBOARD_RESOURCES
 205        bool
 206        default n
 207
 208config USE_OPTION_TABLE
 209        bool
 210        default n
 211
 212config HAVE_OPTION_TABLE
 213        bool
 214        default n
 215        help
 216          This variable specifies whether a given board has a cmos.layout
 217          file containing NVRAM/CMOS bit definitions.
 218          It defaults to 'n' but can be selected in mainboard/*/Kconfig.
 219
 220config PIRQ_ROUTE
 221        bool
 222        default n
 223
 224config HAVE_SMI_HANDLER
 225        bool
 226        default n
 227
 228config PCI_IO_CFG_EXT
 229        bool
 230        default n
 231
 232config IOAPIC
 233        bool
 234        default n
 235
 236# TODO: Can probably be removed once all chipsets have kconfig options for it.
 237config VIDEO_MB
 238        int
 239        default 0
 240
 241config USE_WATCHDOG_ON_BOOT
 242        bool
 243        default n
 244
 245config VGA
 246        bool
 247        default n
 248        help
 249          Build board-specific VGA code.
 250
 251config GFXUMA
 252        bool
 253        default n
 254        help
 255          Enable Unified Memory Architecture for graphics.
 256
 257# TODO
 258# menu "Drivers"
 259#
 260# endmenu
 261
 262config HAVE_ACPI_TABLES
 263        bool
 264        help
 265          This variable specifies whether a given board has ACPI table support.
 266          It is usually set in mainboard/*/Kconfig.
 267          Whether or not the ACPI tables are actually generated by coreboot
 268          is configurable by the user via GENERATE_ACPI_TABLES.
 269
 270config HAVE_MP_TABLE
 271        bool
 272        help
 273          This variable specifies whether a given board has MP table support.
 274          It is usually set in mainboard/*/Kconfig.
 275          Whether or not the MP table is actually generated by coreboot
 276          is configurable by the user via GENERATE_MP_TABLE.
 277
 278config HAVE_PIRQ_TABLE
 279        bool
 280        help
 281          This variable specifies whether a given board has PIRQ table support.
 282          It is usually set in mainboard/*/Kconfig.
 283          Whether or not the PIRQ table is actually generated by coreboot
 284          is configurable by the user via GENERATE_PIRQ_TABLE.
 285
 286#These Options are here to avoid "undefined" warnings.
 287#The actual selection and help texts are in the following menu.
 288
 289config GENERATE_ACPI_TABLES
 290        bool
 291        default HAVE_ACPI_TABLES
 292
 293config GENERATE_MP_TABLE
 294        bool
 295        default HAVE_MP_TABLE
 296
 297config GENERATE_PIRQ_TABLE
 298        bool
 299        default HAVE_PIRQ_TABLE
 300
 301menu "System tables"
 302
 303config WRITE_HIGH_TABLES
 304        bool "Write 'high' tables to avoid being overwritten in F segment"
 305        default y
 306
 307config MULTIBOOT
 308        bool "Generate Multiboot tables (for GRUB2)"
 309        default y
 310
 311config GENERATE_ACPI_TABLES
 312        depends on HAVE_ACPI_TABLES
 313        bool "Generate ACPI tables"
 314        default y
 315        help
 316          Generate ACPI tables for this board.
 317
 318          If unsure, say Y.
 319
 320config GENERATE_MP_TABLE
 321        depends on HAVE_MP_TABLE
 322        bool "Generate an MP table"
 323        default y
 324        help
 325          Generate an MP table (conforming to the Intel MultiProcessor
 326          specification 1.4) for this board.
 327
 328          If unsure, say Y.
 329
 330config GENERATE_PIRQ_TABLE
 331        depends on HAVE_PIRQ_TABLE
 332        bool "Generate a PIRQ table"
 333        default y
 334        help
 335          Generate a PIRQ table for this board.
 336
 337          If unsure, say Y.
 338
 339endmenu
 340
 341menu "Payload"
 342
 343choice
 344        prompt "Add a payload"
 345        default PAYLOAD_NONE if !ARCH_X86
 346        default PAYLOAD_SEABIOS if ARCH_X86
 347
 348config PAYLOAD_NONE
 349        bool "None"
 350        help
 351          Select this option if you want to create an "empty" coreboot
 352          ROM image for a certain mainboard, i.e. a coreboot ROM image
 353          which does not yet contain a payload.
 354
 355          For such an image to be useful, you have to use 'cbfstool'
 356          to add a payload to the ROM image later.
 357
 358config PAYLOAD_ELF
 359        bool "An ELF executable payload"
 360        help
 361          Select this option if you have a payload image (an ELF file)
 362          which coreboot should run as soon as the basic hardware
 363          initialization is completed.
 364
 365          You will be able to specify the location and file name of the
 366          payload image later.
 367
 368config PAYLOAD_SEABIOS
 369        bool "SeaBIOS"
 370        depends on ARCH_X86
 371        help
 372          Select this option if you want to build a coreboot image
 373          with a SeaBIOS payload. If you don't know what this is
 374          about, just leave it enabled.
 375
 376          See http://coreboot.org/Payloads for more information.
 377
 378config PAYLOAD_FILO
 379        bool "FILO"
 380        help
 381          Select this option if you want to build a coreboot image
 382          with a FILO payload. If you don't know what this is
 383          about, just leave it enabled.
 384
 385          See http://coreboot.org/Payloads for more information.
 386
 387endchoice
 388
 389choice
 390        prompt "SeaBIOS version"
 391        default SEABIOS_STABLE
 392        depends on PAYLOAD_SEABIOS
 393
 394config SEABIOS_STABLE
 395        bool "stable"
 396        help
 397          Stable SeaBIOS version
 398config SEABIOS_MASTER
 399        bool "master"
 400        help
 401          Newest SeaBIOS version
 402endchoice
 403
 404choice
 405        prompt "FILO version"
 406        default FILO_STABLE
 407        depends on PAYLOAD_FILO
 408
 409config FILO_STABLE
 410        bool "0.6.0"
 411        help
 412          Stable FILO version
 413config FILO_MASTER
 414        bool "HEAD"
 415        help
 416          Newest FILO version
 417endchoice
 418
 419config PAYLOAD_FILE
 420        string "Payload path and filename"
 421        depends on PAYLOAD_ELF
 422        default "payload.elf"
 423        help
 424          The path and filename of the ELF executable file to use as payload.
 425
 426config PAYLOAD_FILE
 427        depends on PAYLOAD_SEABIOS
 428        default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
 429
 430config PAYLOAD_FILE
 431        depends on PAYLOAD_FILO
 432        default "payloads/external/FILO/filo/build/filo.elf"
 433
 434# TODO: Defined if no payload? Breaks build?
 435config COMPRESSED_PAYLOAD_LZMA
 436        bool "Use LZMA compression for payloads"
 437        default y
 438        depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
 439        help
 440          In order to reduce the size payloads take up in the ROM chip
 441          coreboot can compress them using the LZMA algorithm.
 442
 443config COMPRESSED_PAYLOAD_NRV2B
 444        bool
 445        default n
 446
 447endmenu
 448
 449menu "VGA BIOS"
 450
 451config VGA_BIOS
 452        bool "Add a VGA BIOS image"
 453        help
 454          Select this option if you have a VGA BIOS image that you would
 455          like to add to your ROM.
 456
 457          You will be able to specify the location and file name of the
 458          image later.
 459
 460config VGA_BIOS_FILE
 461        string "VGA BIOS path and filename"
 462        depends on VGA_BIOS
 463        default "vgabios.bin"
 464        help
 465          The path and filename of the file to use as VGA BIOS.
 466
 467config VGA_BIOS_ID
 468        string "VGA device PCI IDs"
 469        depends on VGA_BIOS
 470        default "1106,3230"
 471        help
 472          The comma-separated PCI vendor and device ID that would associate
 473          your VGA BIOS to your video card.
 474
 475          Example: 1106,3230
 476
 477          In the above example 1106 is the PCI vendor ID (in hex, but without
 478          the "0x" prefix) and 3230 specifies the PCI device ID of the
 479          video card (also in hex, without "0x" prefix).
 480
 481config INTEL_MBI
 482        bool "Add an MBI image"
 483        depends on NORTHBRIDGE_INTEL_I82830
 484        help
 485          Select this option if you have an Intel MBI image that you would
 486          like to add to your ROM.
 487
 488          You will be able to specify the location and file name of the
 489          image later.
 490
 491config MBI_FILE
 492        string "Intel MBI path and filename"
 493        depends on INTEL_MBI
 494        default "mbi.bin"
 495        help
 496          The path and filename of the file to use as VGA BIOS.
 497
 498endmenu
 499
 500menu "Bootsplash"
 501        depends on PCI_OPTION_ROM_RUN_YABEL
 502
 503config BOOTSPLASH
 504        prompt "Show graphical bootsplash"
 505        bool
 506        depends on PCI_OPTION_ROM_RUN_YABEL
 507        help
 508          This option shows a graphical bootsplash screen. The grapics are
 509          loaded from the CBFS file bootsplash.jpg.
 510
 511config BOOTSPLASH_FILE
 512        string "Bootsplash path and filename"
 513        depends on BOOTSPLASH
 514        default "bootsplash.jpg"
 515        help
 516          The path and filename of the file to use as graphical bootsplash
 517          screen. The file format has to be jpg.
 518
 519# TODO: Turn this into a "choice".
 520config FRAMEBUFFER_VESA_MODE
 521        prompt "VESA framebuffer video mode"
 522        hex
 523        default 0x117
 524        depends on BOOTSPLASH
 525        help
 526          This option sets the resolution used for the coreboot framebuffer and
 527          bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
 528          some day make this a "choice".
 529
 530config COREBOOT_KEEP_FRAMEBUFFER
 531        prompt "Keep VESA framebuffer"
 532        bool
 533        depends on BOOTSPLASH
 534        help
 535          This option keeps the framebuffer mode set after coreboot finishes
 536          execution. If this option is enabled, coreboot will pass a
 537          framebuffer entry in its coreboot table and the payload will need a
 538          framebuffer driver. If this option is disabled, coreboot will switch
 539          back to text mode before handing control to a payload.
 540
 541endmenu
 542
 543menu "Debugging"
 544
 545# TODO: Better help text and detailed instructions.
 546config GDB_STUB
 547        bool "GDB debugging support"
 548        default y
 549        help
 550          If enabled, you will be able to set breakpoints for gdb debugging.
 551          See src/arch/x86/lib/c_start.S for details.
 552
 553config HAVE_DEBUG_RAM_SETUP
 554        def_bool n
 555
 556config DEBUG_RAM_SETUP
 557        bool "Output verbose RAM init debug messages"
 558        default n
 559        depends on HAVE_DEBUG_RAM_SETUP
 560        help
 561          This option enables additional RAM init related debug messages.
 562          It is recommended to enable this when debugging issues on your
 563          board which might be RAM init related.
 564
 565          Note: This option will increase the size of the coreboot image.
 566
 567          If unsure, say N.
 568
 569config HAVE_DEBUG_CAR
 570        def_bool n
 571
 572config DEBUG_CAR
 573        def_bool n
 574        depends on HAVE_DEBUG_CAR
 575
 576if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
 577# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
 578# printk(BIOS_DEBUG, ...) calls.
 579config DEBUG_CAR
 580        bool "Output verbose Cache-as-RAM debug messages"
 581        default n
 582        depends on HAVE_DEBUG_CAR
 583        help
 584          This option enables additional CAR related debug messages.
 585endif
 586
 587config DEBUG_PIRQ
 588        bool "Check PIRQ table consistency"
 589        default n
 590        depends on GENERATE_PIRQ_TABLE
 591        help
 592          If unsure, say N.
 593
 594config HAVE_DEBUG_SMBUS
 595        def_bool n
 596
 597config DEBUG_SMBUS
 598        bool "Output verbose SMBus debug messages"
 599        default n
 600        depends on HAVE_DEBUG_SMBUS
 601        help
 602          This option enables additional SMBus (and SPD) debug messages.
 603
 604          Note: This option will increase the size of the coreboot image.
 605
 606          If unsure, say N.
 607
 608config DEBUG_SMI
 609        bool "Output verbose SMI debug messages"
 610        default n
 611        depends on HAVE_SMI_HANDLER
 612        help
 613          This option enables additional SMI related debug messages.
 614
 615          Note: This option will increase the size of the coreboot image.
 616
 617          If unsure, say N.
 618
 619config DEBUG_SMM_RELOCATION
 620        bool "Debug SMM relocation code"
 621        default n
 622        depends on HAVE_SMI_HANDLER
 623        help
 624          This option enables additional SMM handler relocation related
 625          debug messages.
 626
 627          Note: This option will increase the size of the coreboot image.
 628
 629          If unsure, say N.
 630
 631config DEBUG_MALLOC
 632        def_bool n
 633
 634# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
 635# printk(BIOS_DEBUG, ...) calls.
 636if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
 637config DEBUG_MALLOC
 638        bool "Output verbose malloc debug messages"
 639        default n
 640        help
 641          This option enables additional malloc related debug messages.
 642
 643          Note: This option will increase the size of the coreboot image.
 644
 645          If unsure, say N.
 646endif
 647
 648config REALMODE_DEBUG
 649        def_bool n
 650        depends on PCI_OPTION_ROM_RUN_REALMODE
 651
 652if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
 653# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
 654# printk(BIOS_DEBUG, ...) calls.
 655config REALMODE_DEBUG
 656        bool "Enable debug messages for option ROM execution"
 657        default n
 658        depends on PCI_OPTION_ROM_RUN_REALMODE
 659        help
 660          This option enables additional x86emu related debug messages.
 661
 662          Note: This option will increase the time to emulate a ROM.
 663
 664          If unsure, say N.
 665endif
 666
 667config X86EMU_DEBUG
 668        bool "Output verbose x86emu debug messages"
 669        default n
 670        depends on PCI_OPTION_ROM_RUN_YABEL
 671        help
 672          This option enables additional x86emu related debug messages.
 673
 674          Note: This option will increase the size of the coreboot image.
 675
 676          If unsure, say N.
 677
 678config X86EMU_DEBUG_JMP
 679        bool "Trace JMP/RETF"
 680        default n
 681        depends on X86EMU_DEBUG
 682        help
 683          Print information about JMP and RETF opcodes from x86emu.
 684
 685          Note: This option will increase the size of the coreboot image.
 686
 687          If unsure, say N.
 688
 689config X86EMU_DEBUG_TRACE
 690        bool "Trace all opcodes"
 691        default n
 692        depends on X86EMU_DEBUG
 693        help
 694          Print _all_ opcodes that are executed by x86emu.
 695
 696          WARNING: This will produce a LOT of output and take a long time.
 697
 698          Note: This option will increase the size of the coreboot image.
 699
 700          If unsure, say N.
 701
 702config X86EMU_DEBUG_PNP
 703        bool "Log Plug&Play accesses"
 704        default n
 705        depends on X86EMU_DEBUG
 706        help
 707          Print Plug And Play accesses made by option ROMs.
 708
 709          Note: This option will increase the size of the coreboot image.
 710
 711          If unsure, say N.
 712
 713config X86EMU_DEBUG_DISK
 714        bool "Log Disk I/O"
 715        default n
 716        depends on X86EMU_DEBUG
 717        help
 718          Print Disk I/O related messages.
 719
 720          Note: This option will increase the size of the coreboot image.
 721
 722          If unsure, say N.
 723
 724config X86EMU_DEBUG_PMM
 725        bool "Log PMM"
 726        default n
 727        depends on X86EMU_DEBUG
 728        help
 729          Print messages related to POST Memory Manager (PMM).
 730
 731          Note: This option will increase the size of the coreboot image.
 732
 733          If unsure, say N.
 734
 735
 736config X86EMU_DEBUG_VBE
 737        bool "Debug VESA BIOS Extensions"
 738        default n
 739        depends on X86EMU_DEBUG
 740        help
 741          Print messages related to VESA BIOS Extension (VBE) functions.
 742
 743          Note: This option will increase the size of the coreboot image.
 744
 745          If unsure, say N.
 746
 747config X86EMU_DEBUG_INT10
 748        bool "Redirect INT10 output to console"
 749        default n
 750        depends on X86EMU_DEBUG
 751        help
 752          Let INT10 (i.e. character output) calls print messages to debug output.
 753
 754          Note: This option will increase the size of the coreboot image.
 755
 756          If unsure, say N.
 757
 758config X86EMU_DEBUG_INTERRUPTS
 759        bool "Log intXX calls"
 760        default n
 761        depends on X86EMU_DEBUG
 762        help
 763          Print messages related to interrupt handling.
 764
 765          Note: This option will increase the size of the coreboot image.
 766
 767          If unsure, say N.
 768
 769config X86EMU_DEBUG_CHECK_VMEM_ACCESS
 770        bool "Log special memory accesses"
 771        default n
 772        depends on X86EMU_DEBUG
 773        help
 774          Print messages related to accesses to certain areas of the virtual
 775          memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
 776
 777          Note: This option will increase the size of the coreboot image.
 778
 779          If unsure, say N.
 780
 781config X86EMU_DEBUG_MEM
 782        bool "Log all memory accesses"
 783        default n
 784        depends on X86EMU_DEBUG
 785        help
 786          Print memory accesses made by option ROM.
 787          Note: This also includes accesses to fetch instructions.
 788
 789          Note: This option will increase the size of the coreboot image.
 790
 791          If unsure, say N.
 792
 793config X86EMU_DEBUG_IO
 794        bool "Log IO accesses"
 795        default n
 796        depends on X86EMU_DEBUG
 797        help
 798          Print I/O accesses made by option ROM.
 799
 800          Note: This option will increase the size of the coreboot image.
 801
 802          If unsure, say N.
 803
 804config LLSHELL
 805        bool "Built-in low-level shell"
 806        default n
 807        help
 808          If enabled, you will have a low level shell to examine your machine.
 809          Put llshell() in your (romstage) code to start the shell.
 810          See src/arch/x86/llshell/llshell.inc for details.
 811
 812endmenu
 813
 814config LIFT_BSP_APIC_ID
 815        bool
 816        default n
 817
 818# These probably belong somewhere else, but they are needed somewhere.
 819config AP_CODE_IN_CAR
 820        bool
 821        default n
 822
 823config RAMINIT_SYSINFO
 824        bool
 825        default n
 826
 827config ENABLE_APIC_EXT_ID
 828        bool
 829        default n
 830
 831config WARNINGS_ARE_ERRORS
 832        bool
 833        default y
 834
 835config ID_SECTION_OFFSET
 836        hex
 837        default 0x10
 838
 839# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
 840# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
 841# mutually exclusive. One of these options must be selected in the
 842# mainboard Kconfig if the chipset supports enabling and disabling of
 843# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
 844# in mainboard/Kconfig to know if the button should be enabled or not.
 845
 846config POWER_BUTTON_DEFAULT_ENABLE
 847        def_bool n
 848        help
 849          Select when the board has a power button which can optionally be
 850          disabled by the user.
 851
 852config POWER_BUTTON_DEFAULT_DISABLE
 853        def_bool n
 854        help
 855          Select when the board has a power button which can optionally be
 856          enabled by the user, e.g. when the board ships with a jumper over
 857          the power switch contacts.
 858
 859config POWER_BUTTON_FORCE_ENABLE
 860        def_bool n
 861        help
 862          Select when the board requires that the power button is always
 863          enabled.
 864
 865config POWER_BUTTON_FORCE_DISABLE
 866        def_bool n
 867        help
 868          Select when the board requires that the power button is always
 869          disabled, e.g. when it has been hardwired to ground.
 870
 871config POWER_BUTTON_IS_OPTIONAL
 872        bool
 873        default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
 874        default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
 875        help
 876          Internal option that controls ENABLE_POWER_BUTTON visibility.
 877
 878source src/Kconfig.deprecated_options
 879
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